MTB15N06V
Designer’s™ Data Sheet
TMOS V™
Power Field Effect
Transistor
D
2
PAK for Surface Mount
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N−Channel Enhancement−Mode Silicon
Gate
TMOS V is a new technology designed to achieve an on−resistance
area product about one−half that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50 and 60
volt TMOS devices. Just as with our TMOS E−FET designs, TMOS V
is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed switching
applications in power supplies, converters and power motor controls,
these devices are particularly well suited for bridge circuits where
diode speed and commutating safe operating areas are critical and
offer additional safety margin against unexpected voltage transients.
New Features of TMOS V
TMOS POWER FET
15 AMPERES, 60 VOLTS
R
DS(on)
= 0.12
W
D
2
PAK
CASE 418B−02,
Style 2
D
•
On−resistance Area Product about One−half that of Standard
Features Common to TMOS V and TMOS E−FETs
G
TM
MOSFETs with New Low Voltage, Low R
DS(on)
Technology
•
Faster Switching than E−FET Predecessors
S
•
•
•
•
Avalanche Energy Specified
I
DSS
and V
DS(on)
Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS E−FET
Surface Mount Package Available in 16 mm 13−inch/2500 Unit Tape
& Reel, Add T4 Suffix to Part Number
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 3
1
Publication Order Number:
MTB15N06V/D
MTB15N06V
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−Source Voltage
Drain−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−Source Voltage — Continuous
Gate−Source Voltage
— Non−Repetitive (t
p
≤
10 ms)
Drain Current — Continuous @ 25°C
Drain Current
— Continuous @ 100°C
Drain Current
— Single Pulse (t
p
≤
10
μs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ T
A
= 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy — Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 10 Vdc, I
L
= 15 Apk, L = 1.0 mH, R
G
= 25
Ω)
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Thermal Resistance
— Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
Value
60
60
±
20
±
25
15
8.7
45
55
0.37
3.0
−
55 to 175
113
2.73
62.5
50
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
I
DM
P
D
T
J
, T
stg
E
AS
R
θJC
R
θJA
R
θJA
T
L
°C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
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MTB15N06V
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 60 Vdc, V
GS
= 0 Vdc)
(V
DS
= 60 Vdc, V
GS
= 0 Vdc, T
J
= 150°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
μAdc)
Temperature Coefficient (Negative)
Static Drain−Source On−Resistance (V
GS
= 10 Vdc, I
D
= 7.5 Adc)
Drain−Source On−Voltage (V
GS
= 10 Vdc)
(I
D
= 15 Adc)
(I
D
= 7.5 Adc, T
J
= 150°C)
Forward Transconductance (V
DS
= 8.0 Vdc, I
D
= 7.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(V
DD
= 30 Vdc, I
D
= 15 Adc,
V
GS
= 10 Vdc,
R
G
= 9.1
Ω)
t
d(on)
t
r
t
d(off)
t
f
Q
T
(V
DS
= 48 Vdc, I
D
= 15 Adc,
V
GS
= 10 Vdc)
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (1)
(I
S
= 15 Adc, V
GS
= 0 Vdc)
(I
S
= 15 Adc, V
GS
= 0 Vdc, T
J
= 150°C)
V
SD
Vdc
—
—
—
—
—
—
—
—
1.05
0.9
59.3
46
13.3
0.165
4.5
7.5
1.6
—
—
—
—
—
—
—
μC
nH
nH
ns
—
—
—
—
—
—
—
—
7.6
51
18
33
14.4
2.8
6.4
6.1
20
100
40
70
20
—
—
—
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
—
—
—
469
148
35
660
200
60
pF
V
GS(th)
2.0
—
—
—
—
4.0
2.7
5.0
0.08
2.0
—
6.2
4.0
—
0.12
2.2
1.9
—
mhos
Vdc
mV/°C
Ohm
Vdc
V
(BR)DSS
60
—
—
—
—
—
67
—
—
—
—
—
10
100
100
Vdc
mV/°C
μAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
R
DS(on)
V
DS(on)
g
FS
Reverse Recovery Time
(See Figure 14)
t
rr
(I
S
= 15 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/μs)
t
a
t
b
Q
RR
L
D
L
S
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width
≤
300
μs,
Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
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MTB15N06V
TYPICAL ELECTRICAL CHARACTERISTICS
30
25
20
15
10
5
0
5V
T
J
= 25°C
V
GS
= 10 V
9V
30
8V
7V
I D , DRAIN CURRENT (AMPS)
25
100°C
20
15
10
5
0
25°C
T
J
= − 55°C
V
DS
≥
10 V
6V
0
1
2
3
4
5
6
7
2
4
6
8
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.2
V
GS
= 10 V
0.13
T
J
= 25°C
0.11
0.14
T
J
= 100°C
0.09
V
GS
= 10 V
25°C
0.08
− 55°C
( )
0.07
15 V
0.02
0
5
10
15
20
25
30
0.05
0
5
10
15
20
25
30
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2
V
GS
= 10 V
I
D
= 7.5 A
1.6
I DSS , LEAKAGE (nA)
100
V
GS
= 0 V
1.2
T
J
= 125°C
0.8
0.4
− 50
− 25
0
25
50
75
100
125
150
175
10
0
10
20
30
40
50
60
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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MTB15N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by r ec ogniz ing that the powe r MO S FET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate
of average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
1500
1200
C, CAPACITANCE (pF)
V
DS
= 0 V
C
iss
V
GS
= 0 V
T
J
= 25°C
The capacitance (C
iss
) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to
the on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
inductive; the data in the figure is taken with a resistive load,
which approximates an optimally snubbed inductive load.
Power MOSFETs may be safely operated into an inductive
load; however, snubbing reduces switching losses.
900
C
rss
600
C
iss
C
oss
C
rss
0
10
5
V
GS
0
V
DS
5
10
15
20
25
300
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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Altera SoC
