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MTD6N20E
Preferred Device
Power MOSFET
6 Amps, 200 Volts
N−Channel DPAK
This advanced Power MOSFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain−to−source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor controls,
these devices are particularly well suited for bridge circuits where
diode speed and commutating safe operating areas are critical and
offer additional safety margin against unexpected voltage transients.
Features
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6 AMPERES, 200 VOLTS
R
DS(on)
= 460 mW
N−Channel
D
•
Avalanche Energy Specified
•
Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
•
Diode is Characterized for Use in Bridge Circuits
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
•
Pb−Free Package is Available*
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MW)
Gate−to−Source Voltage
− Continuous
− Non−repetitive (t
p
≤
10 ms)
Drain Current
− Continuous
− Continuous @ 100°C
− Single Pulse (t
p
≤
10
ms)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ T
A
= 25°C (Note 2)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 80 Vdc, V
GS
= 10 Vdc,
I
L
= 6.0 Apk, L = 3.0 mH, R
G
= 25
W)
Thermal Resistance − Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
I
DM
P
D
Value
200
200
±
20
±
40
6.0
3.8
18
50
0.4
1.75
−55 to
150
54
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
W
W/°C
W
°C
mJ
1
2
3
1 2 3
Gate Drain Source
Device Code
= Year
= Work Week
= Pb−Free Package
4
DPAK
CASE 369D
STYLE 2
4 Drain
YWW
6
N20E
1 2
3
1
Gate
2
Drain
3
Source
4
DPAK
CASE 369C
STYLE 2
G
S
MARKING
DIAGRAMS
4 Drain
YWW
6
N20EG
T
J
, T
stg
E
AS
R
qJC
R
qJA
R
qJA
2.50
100
71.4
°C/W
Maximum Temperature for Soldering
T
L
260
°C
Purposes, 1/8″ from case for 10 secs
ORDERING INFORMATION
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
See detailed ordering and shipping information in the package
normal operating conditions) and are not valid simultaneously. If these limits are
dimensions section on page 7 of this data sheet.
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
Preferred
devices are recommended choices for future use
1. When surface mounted to an FR4 board using the minimum recommended
and best overall value.
pad size.
2. When surface mounted to an FR4 board using the 0.5 sq. in. drain pad size.
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
6N20E
Y
WW
G
©
Semiconductor Components Industries, LLC, 2005
1
August, 2005 − Rev. 3
Publication Order Number:
MTD6N20E/D
MTD6N20E
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25
mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 200 Vdc, V
GS
= 0 Vdc)
(V
DS
= 200 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0)
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
mAdc)
Temperature Coefficient (Negative)
Static Drain−Source On−Resistance (V
GS
= 10 Vdc, I
D
= 3.0 Adc)
Drain−Source On−Voltage (V
GS
= 10 Vdc)
(I
D
= 6.0 Adc)
(I
D
= 3.0 Adc, T
J
= 125°C)
Forward Transconductance (V
DS
= 15 Vdc, I
D
= 3.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(V
DS
= 160 Vdc, I
D
= 6.0 Adc,
V
GS
= 10 Vdc)
(V
DD
= 100 Vdc, I
D
= 6.0 Adc,
V
GS
= 10 Vdc,
R
G
= 9.1
W)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 3)
(I
S
= 6.0 Adc, V
GS
= 0 Vdc)
(I
S
= 6.0 Adc, V
GS
= 0 Vdc,
T
J
= 125°C)
V
SD
−
−
t
rr
(I
S
= 6.0 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/ms)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
3. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
4. Switching characteristics are independent of operating junction temperature.
L
D
L
S
−
−
4.5
7.5
−
−
nH
nH
t
a
t
b
Q
RR
−
−
−
−
0.99
0.9
138
93
45
0.74
1.2
−
−
−
−
−
mC
ns
Vdc
−
−
−
−
−
−
−
−
8.8
29
22
20
13.7
2.7
7.1
5.9
17.6
58
44
40.8
21
−
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
342
92
27
480
130
55
pF
V
GS(th)
2.0
−
R
DS(on)
V
DS(on)
−
−
g
FS
1.5
2.9
−
−
5.0
4.4
−
mhos
−
3.0
7.1
0.46
4.0
−
0.700
Vdc
mV/°C
Ohm
Vdc
V
(BR)DSS
200
−
I
DSS
−
−
I
GSS
−
−
−
−
10
100
100
nAdc
−
689
−
−
Vdc
mV/°C
mAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
(See Figure 14)
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2
MTD6N20E
TYPICAL ELECTRICAL CHARACTERISTICS
12
T
J
= 25°C
I D , DRAIN CURRENT (AMPS)
10
8
6
4
2
0
6V
12
I D , DRAIN CURRENT (AMPS)
10
8
6
4
2
0
V
GS
= 10 V
9V
8V
7V
V
DS
≥
10 V
T
J
= −55°C
25°C
100°C
5V
0
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
1.2
V
GS
= 10 V
1.0
0.8
0.6
0.4
0.2
0
T
J
= 100°C
0.70
T
J
= 25°C
0.65
0.60
0.55
0.50
0.45
0.40
15 V
25°C
−55
°C
V
GS
= 10 V
0
2
4
6
8
10
12
0
2
4
6
8
10
12
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
R DS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2.5
2.0
V
GS
= 10 V
I
D
= 3 A
I DSS , LEAKAGE (nA)
100
V
GS
= 0 V
T
J
= 125°C
100°C
10
1.5
1.0
0.5
25°C
0
− 50
− 25
0
25
50
75
100
125
150
1
0
50
100
150
200
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
MTD6N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
900
750
C, CAPACITANCE (pF)
600
450
300
C
oss
150
0
C
rss
10
5
V
GS
0
V
DS
5
10
15
20
25
C
iss
C
iss
V
DS
= 0 V
V
GS
= 0 V
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
T
J
= 25°C
C
rss
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
