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Preliminary Data Sheet

WidePort LANCAM

Family

APPLICATION BENEFITS

Enhances Ethernet and Token-Ring LAN bridges

and switches:

64-bit width stores 48-bit MAC address plus

associated data (Port ID, time stamp,

“permanent” flag)

32-bit I/O supports multiple ports of fast

(100 Mb) Ethernet or Gigabit Ethernet

Station list depth flexibility with choice of

pin-compatible device densities and

glue-free cascading

3.3 Volt option for low power systems

Industrial temperature grades for harsh

environments

DISTINCTIVE CHARACTERISTICS

4096 (4485A/L), 2048 (2485A/L), and 1024

(1485A/L) word CMOS content-addressable

memories (CAMs)

64-bit word width

32-bit I/O compatible with the MU9C1485

Fast 50 ns compare speed

Dual configuration register set for rapid

context switching

Increased flexibility of MUSIC’s patented

CAM/RAM partitioning

80-pin TQFP package with the same pinout as

the MU9C1485 and MU9C1965A/L

5 volt (A) or 3.3 volt (L) operation

(3 2 )

M UX

D ATA (6 4 )

I/ O B U FF E R S

DQ 3 1 – 0

(3 2 )

TRA N S L A TE

(8 02 .3 /8 0 2 .5 )

DE M U X

D ATA (6 4 )

(3 2 )

S O U R CE AN D

D E S TINA TIO N

S EG M ENT

C O U N TE R S

C O M P AR A ND

M AS K R E G IS TE R 1

M AS K R E G IS TE R 2

3 2 K o r 1 6 K X 2 V AL ID I TY B ITS

C O MM AN D S

& S TA TU S

AD D R E S S D E C O D E R

/CM

/EC

/R E S E T

17/ 16

/M A

P R I OR I TY E N CO D E R

/M M

CO NT RO L

LO G I C

CO NT RO L

AND S T AT US

RE G IS T ER S

CAM A RR AY

3 2 K or 1 6 K

W O RD S

X 6 4 B ITS

15/ 14

/ FF

F LA G

L O G IC

/ FI

/M F

/M I

Block Diagram

LANCAM, the MUSIC logo, and the phrase “MUSIC Semiconductors” are registered trademarks of MUSIC Semiconductors. MUSIC is

a trademark of MUSIC Semiconductors. Certain features of this device are patented under US Patent 5,383,146.

2 December 1998 Rev. 2

WidePort LANCAM

Family

GENERAL DESCRIPTION

The MU9C4485A/L, MU9C2485A/L, and MU9C1485A/L

WidePort LANCAMs are 64-bit wide content-addressable

memories (CAMs), featuring a 32-bit wide interface. This

interface doubles the available I/O bandwidth in many

applications while maintaining the same powerful enhanced

architecture and instruction set as the MU9C2480A/L.

Content-addressable memories, also known as associative

memories, operate in the converse way to random access

memories (RAM). In a RAM, the input to the device is an

address and the output is the data stored at that address. In a

CAM, the input is a data sample and the output is a flag to

indicate a match and the address of the matching data. As a

result, a CAM searches large databases for matching data in a

short, constant time period, no matter how many entries are in

the database. The ability to search data words up to 64 bits

wide allows large address spaces to be searched rapidly and

efficiently. A patented architecture links each CAM entry to

associated data and makes this data available for use after a

successful compare operation.

While the WidePort LANCAMs are optimized for LAN network

address filtering, they are also well suited for applications that

require high-speed data searching, such as virtual memories

and cache management, data compression and encryption,

database accelerators, and image processing.

OPERATIONAL OVERVIEW

To use the WidePort LANCAM, the user loads the data into

the Comparand register, which is automatically compared to

all valid CAM locations. The device then indicates whether

or not one or more of the valid CAM locations contains data

that match the target data. The status of each CAM location

is determined by two validity bits at each memory location.

The two bits are encoded to render four validity conditions:

Valid, Skip, Empty, and Random Access, as shown in Table 1.

The memory can be partitioned into CAM and associated

RAM segments on 16-bit boundaries, but by using one of the

two available mask registers, the CAM/RAM partitioning can

be set at any arbitrary size between zero and 64 bits.

The WidePort LANCAM’s internal data path is 64 bits wide

for rapid internal comparison and data movement. A data

translation facility converts between IEEE 802.3 (CSMA/CD

“Ethernet”) and 802.5 (Token Ring) address formats. Vertical

cascading of additional WidePort LANCAMs in a daisy chain

fashion extends the CAM memory depth for large databases.

Cascading requires no external logic. Loading data to the

Control, Comparand, and mask registers automatically triggers

Skip Bit

Empty Bit

Entry Type

Valid

Empty

Skip

RAM

a compare. Compares may also be initiated by a command to

the device. Associated RAM data is available immediately

after a successful compare operation. The Status register reports

the results of compares including all flags and addresses. Two

mask registers are available and can be used in two different

ways: to mask comparisons or to mask data writes. The random

access validity type allows additional masks to be stored in

the CAM array where they may be retrieved rapidly.

A simple four-wire control interface and commands loaded

into the Instruction decoder control the device. A powerful

instruction set increases the control flexibility and minimizes

software overhead. Additionally, dedicated pins for match and

multiple-match flags enhance performance when the device is

controlled by a state machine. These and other features make

the WidePort LANCAM a powerful associative memory that

drastically reduces search delays.

G ND

D Q8

D Q7

D Q6

D Q5

D Q4

D Q3

D Q2

D Q1

D Q0

G ND

V CC

/C M

/ MA

/EC

/ FI

G ND

D Q9

D Q 10

D Q 11

V CC

TE S T2

G ND

D Q 12

D Q 13

G ND

/ FF

/ MI

/ MF

/ MM

G ND

/R ESET

V CC

TE S T1

D Q 31

D Q 30

G ND

80-Pin TQFP

8 0 -P IN TQ FP

(Top V ie w )

(Top View)

Table 1: Entry Types vs. Validity Bits

LOW

HIGH

/CM

Cycle Type

LOW

Command Write Cycle

HIGH

Data Write Cycle

LOW

Command Read Cycle

HIGH

Data Read Cycle

Table 2: I/O Cycles

D Q 14

D Q 15

D Q 16

D Q 28

D Q 29

D Q 17

D Q 18

D Q 19

D Q 20

V CC

D Q 21

D Q 22

D Q 23

D Q 24

D Q 25

D Q 26

D Q 27

Pinout Diagram

Rev. 2

WidePort LANCAM

Family

PIN DESCRIPTIONS

All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs

should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout

and bypassing techniques. Refer to the Electrical Characteristics section for more information.

/E (Chip Enable, Input, TTL)

The /E input enables the device while LOW. The falling

edge registers the control signals /W, /CM, /EC. The rising

edge locks the daisy chain, turns off the DQ pins, and clocks

the Destination and Source Segment counters. The four

cycle types enabled by /E are shown in Table 2.

/W (Write Enable, Input, TTL)

The /W input selects the direction of data flow during a

device cycle. /W LOW selects a Write cycle and /W HIGH

selects a Read cycle.

/CM (Data/Command Select, Input, TTL)

The /CM input selects whether the input signals on

DQ31–0 are data or commands. /CM LOW selects Command

cycles and /CM HIGH selects Data cycles.

/EC (Enable Daisy Chain, Input, TTL)

The /EC signal performs two functions. The /EC input

enables the /MF output to show the results of a comparison,

as shown in Figure 6. If /EC is LOW at the falling edge of /E

in a given cycle, the /MF output is enabled. Otherwise, the

/MF output is held HIGH. The /EC signal also enables the

/MF–/MI daisy chain, which serves to select the device

with the highest-priority match in a string of LANCAMs.

Tables 6a and 6b explain the effect of the /EC signal on a

device with or without a match in both Standard and

Enhanced modes. /EC must be HIGH during initialization.

DQ31–0 (Data Bus, Three-state I/O, TTL)

The DQ31–0 lines convey data, commands, and status to

and from the WidePort LANCAM, as shown in Table 3. /W

and /CM control the direction and nature of the information

that flows to or from the device. When /E is HIGH, DQ31–0 go

to HIGH-Z.

/MF (Match Flag, Output, TTL)

The /MF output goes LOW when one or more valid

matches occur during a compare cycle. /MF becomes

valid after /E goes HIGH on the cycle that enables the

daisy chain (on the first cycle that /EC is registered LOW

by the previous falling edge of /E; see Figure 6). In a

daisy chain, valid match(es) in higher priority devices

are passed from the /MI input to /MF. If the daisy chain

is enabled but the match flag is disabled in the Control

of the device (/MF=/MI). /MF is HIGH if there is no match

or when the daisy chain is disabled (/E goes HIGH when

/EC was HIGH on the previous falling edge of /E). The

System Match flag is the /MF pin of the last device in

the daisy chain. /MF will be reset when the active

configuration register set is changed.

/MI (Match Input, Input, TTL)

The /MI input prioritizes devices in vertically cascaded

systems. It is connected to the /MF output of the previous

device in the daisy chain. The /MI pin on the first device in

the chain must be tied HIGH.

/MA (Device Match Flag, Output, TTL)

The /MA output is LOW when one or more valid matches

occur during the current or the last previous compare

cycle. The /MA output is not qualified by /EC or /MI,

and reflects the match flag from that specific device’s

Status register. /MA will be reset when the active register

set is changed.

/MM (Device Multiple Match Flag, Output, TTL)

The /MM output is LOW when more than one valid

match occurs during the current or the last previous

compare cycle. The /MM output is not qualified by /EC

or /MI, and reflects the multiple match flag from that

specific device’s Status register. /MM will be reset when

the active register set is changed.

/FF (Full Flag, Output, TTL)

If enabled in the Control register, the /FF output goes LOW

when no empty memory locations exist within the device

(and in the daisy chain above the device as indicated by

the /FI pin). The System Full flag is the /FF pin of the last

device in the daisy chain, and the Next Free address resides

in the device with /FI LOW and /FF HIGH. If disabled in the

Control register, the /FF output only depends on the /FI

input (/FF = /FI).

/FI (Full Input, Input, TTL)

The /FI input generates a CAM-Memory-System-Full

indication in vertically cascaded systems. It is connected

to the /FF output of the previous device in the daisy chain.

The /FI pin on the first device in a chain must be tied LOW.

Rev. 2

WidePort LANCAM

Family

PIN DESCRIPTIONS

Continued

/RESET (Reset, Input, TTL)

/RESET must be driven LOW to place the device in a known

state before operation, which will reset the device to the

conditions shown in Table 5. The /RESET pin should be

driven by TTL levels, not directly by an RC timeout. /E

must be kept HIGH during /RESET.

TEST1, TEST2 (Test, Input, TTL)

These pins enable MUSIC production test modes that are

not usable in an application. They should be connected to

ground, either directly or through a pull-down resistor, or

they may be left unconnected. These pins may not be

implemented on all versions of these products.

VCC, GND (Positive Power Supply, Ground)

These pins are the power supply connections to the

WidePort LANCAM. VCC must meet the voltage supply

requirements in the Operating Conditions section relative

to the GND pins, which are at 0 Volts (system reference

potential), for correct operation of the device. All the

ground and power pins must be connected to their

respective planes with adequate bulk and high frequency

bypassing capacitors in close proximity to the device.

The MU9C2485A/L and MU9C1485A/L are compatible

with the original MU9C1485 connections, and may be

operated at -90 or slower switching characteristics

without the GND connections on pins 1, 2, 20, 21, 22, 41,

42, 60, 61, and 62.

FUNCTIONAL DESCRIPTION

The WidePort LANCAM is a content-addressable

memory (CAM) with 32-bit I/O for network address

filtering, virtual memory, data compression, caching, and

table lookup applications. The memory consists of static

CAM, organized in 64-bit data fields. Each data field can

be partitioned into a CAM and a RAM subfield on 16-bit

boundaries. The contents of the memory can be randomly

accessed or associatively accessed by the use of a

compare. During automatic comparison cycles, data in

the Comparand register is automatically compared with

the “Valid” entries in the memory array. The Device ID can be

read using a TCO PS instruction (see Table 13).

The data inputs and outputs of the WidePort LANCAM

are multiplexed for data and instructions over a 32-bit

I/O bus. Internally, data is handled on a 64-bit basis,

since the Comparand register, the mask registers, and

each memory entry are 64 bits wide. Memory entries are

LOW

/CM

LOW

Cycle Type

Command write

“f” Bit

globally configurable into CAM and RAM segments on

16-bit boundaries, as described in US Patent 5,383,146

assigned to MUSIC Semiconductors. Seven different

CAM/RAM splits are possible, with the CAM width

going from one to four segments, and the remaining RAM

width going from three to zero segments. Finer resolution

on compare width is possible by invoking a mask register

during a compare, which does global masking on a bit

basis. The CAM subfield contains the associative data,

which enters into compares, while the RAM subfield

contains the associated data, which is not compared. In

LAN bridges, the RAM subfield can hold, for example,

port-address and aging information related to the

destination or source address information held in the

CAM subfield of a given location. In a translation

application, the CAM field can hold the dictionary

entries, while the RAM field holds the translations, with

almost instantaneous response.

DQ31–16

Non-TCO Instruction

TCO Instruction (Read register)*

TCO Instruction (Write register)

Status Register bits 31–16

Status Register bits 31–16†

Data to CR, MRX, Mem.

Data from CR, MRX, Mem.

DQ15–0

XXXX

Absolute Address

XXXX

Value to Register

Status Register bits 15–0

Data to CR, MRX, Mem.

Data from CR, MRX, Mem.

HIGH

LOW

HIGH

Notes:

LOW

HIGH

Command read

TCO 2nd cycle

Data write

Data read

A CW of a TCO Instruction with the “f” bit set to 0 sets up a Register read in the following cycle. The

following cycle must be a Command Read cycle, otherwise the register read will be cancelled.

†

Upper 16 bits will be Status Register bits 31–16, except for a read of the Page Address register, in which

case they will be all zeros.

Table 3: DQ Bus Multiplexing

Rev. 2

WidePort LANCAM

Family

FUNCTIONAL DESCRIPTION

Continued

Each entry has two validity bits (known as Skip bit and

Empty bit) associated with it to define its particular type:

empty, valid, skip, or RAM. When data is written to the

active Comparand register, and the active Segment

Control register reaches its terminal count, the contents

of the Comparand register are automatically compared

with the CAM portion of all the valid entries in the

memory array. For added versatility, the Comparand

time. A Compare instruction can then be used to force

another compare between the Comparand register and

the CAM portion of memory entries of any one of the

four validity types. After a Read or Move from Memory

operation, the validity bits of the location read or moved

will be copied into the Status register, where they can be

read from the Status register using Command Read cycles.

Data can be moved from one of the data registers (CR,

MR1, or MR2) to a memory location that is based on the

results of the last comparison (Highest-Priority Match

or Next Free), or to an absolute address, or to the location

pointed to by the active Address register. Data can also

be written directly to the memory from the DQ bus using

any of the above addressing modes. The Address

increment or decrement, allowing DMA-type reading or

writing from memory.

Two sets of configuration registers (Control, Segment

Control, Address, Mask Register 1, and Persistent Source

and Destination) are provided to permit rapid context

switching between foreground and background

activities. Writes, reads, moves, and compares are

controlled by the currently active set of configuration

registers. The foreground set would typically be pre-

loaded with values useful for comparing input data, often

called filtering, while the background set would be pre-

loaded with values useful for housekeeping activities

such as purging old entries. Moving from the foreground

task of filtering to the background task of purging can

be done by issuing a single instruction to change the

current set of configuration registers. The match

condition of the device is reset whenever the active

The active Control register determines the operating

conditions within the device. Conditions set by this

flag, enable or disable Full flag, default data translation,

CAM/RAM partitioning, disable or select masking

conditions, disable or select auto-incrementing or

auto-decrementing the Address register, and select

Standard (compatible with the MU9C1485) or Enhanced

mode. The active Segment Control register contains

separate counters to control the writing of 32-bit data

segments to the selected persistent destination, and to

control the reading of 32-bit data segments from the

selected persistent source.

There are two active mask registers at any one time,

which can be selected to mask comparisons or data

writes. Mask Register 1 has both a foreground and

background mode to support rapid context switching.

Mask Register 2 does not have this mode, but can be

shifted left or right one bit at a time. For masking

comparisons, data stored in the active selected mask

compared against the valid contents of the memory. If a

bit is set HIGH in the mask register, the same bit position

in the Comparand register becomes a “don’t care” for

the purpose of the comparison with all the memory

locations. During a Data Write cycle or a MOV instruction,

data in the specified active mask register can also

determine which bits in the destination will be updated.

If a bit is HIGH in the mask register, the corresponding

bit of the destination is unchanged.

The match line associated with each memory address is

fed into a priority encoder where multiple responses are

resolved, and the address of the highest-priority

responder (the lowest numerical match address) is

generated. In the LAN bridge application, a multiple

response might indicate an error. In other applications

the existence of multiple responders may be valid.

Four input control signals and commands loaded into an

instruction decoder control the WidePort LANCAM. Two

of the four input control signals determine the cycle type.

The control signals tell the device whether the data on the

I/O bus represents data or a command, and is input or output.

Commands are decoded by instruction logic and control

moves, forced compares, validity bit manipulations, and the

data path within the device. Registers (Control, Segment

Control, Address, Next Free Address, etc.) are accessed using

Temporary Command Override instructions. The data path

from the DQ bus to/from data resources (comparand, masks,

and memory) within the device are set until changed by Select

Persistent Source and Destination instructions.

After a Compare cycle (caused by either a data write to the

Comparand or mask registers, a write to the Control register,

or a forced compare), the Status register contains the

Rev. 2