Data Sheet
MU9C Routing CoProcessor (RCP) Family
APPLICATION BENEFITS
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Longest Prefix Match searches of IPv4 addresses
28 Million IPv4 packets per second supports up to 18
Gb Ethernet or 7 OC-48 ATM ports at wire speed
Longest Prefix Match searches of IPv4 addresses
Exact match on MAC addresses
Processes DA and SA within 190 ns, supporting three
ports of 1 Gb or 34 ports of 100 Mb Ethernet at wire
speed
Mixed mode L3 and L2 single search engine for two
ports at 1 Gb or 29 ports of 100 Mb Ethernet at wire
speed
Directly addresses external RAM containing
associated data of any width
Hardware control states directly address memory and
registers; Instruction and Status registers for optional
software control
DISTINCTIVE CHARACTERISTICS
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4K and 8K x 64-bit words
32-bit ternary or 64-bit binary compares
64-bit per word memory organization
35 ns deterministic compare and output time
32-bit Data I/O port
16-bit Match Address Output port
Address/Control bus directly controls device
operations for faster operation or higher throughput
Seven selectable mask registers
Synchronous operation
Cascadable for increased depth
Extensive set of control states for flexibility
JTAG interface
100-pin and 128-pin LQFP packages; 3.3 Volt
operation (also available in lead-free packages)
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DQ31-0
/VB
/E
/CS1
/CS2
/W
/OE
/AV
AC Bus
/DSC
/RESET
TCLK
TMS
TDI
TDO
/TRST
4K x 64 Word
(MU9CK64)
8K x 64 Word
(MU9C8K64)
Address Database
CONTROL
AND
ADDRESS
DECODER
COMPARAND REGISTER
MASK REGISTER 1-7
ADDRESS REGISTER
CONFIGURATION REGISTER
STATUS REGISTER
INSTRUCTION DECODER
DEVICE SELECT REGISTER
PRIORITY
ENCODER
AND
FLAG
LOGIC
/FI
/FF
/MI
/MF
MM
PA3:0
AA Bus
Figure 1: Block Diagram
MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are
Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of
MUSIC Semiconductors.
March 28, 2007 Rev. 8.10
MU9C Routing CoProcessor (RCP) Family
General Description
GENERAL DESCRIPTION
The MU9C RCP family consists of 4K and 8K x 64-bit
Routing CoProcessors (RCPs) with a 32-bit wide data
interface and a 32-bit ternary compare instruction. The
device is designed for use in layer 3 switches, routers, and
layer 2 switches to provide very high throughput address
translation using tables held in external RAM. The MU9C
RCP has a fully deterministic search time, independent of
the size of the list and the position of the data in the list.
This unique feature guarantees that the wire speed address
recognition does not impact the latency or induce some
jitter on the latency of the global system. Address fields
from the packet header are compared against a list of
entries stored in the array. As a result of the comparison,
the MU9C RCP generates an index that is used to access
an external RAM where port mapping data and other
associated information is stored.
A set of control states provides a powerful and flexible
control interface to the MU9C RCP. This control structure
allows memory read and write, register read and write,
data move, comparison, validity control, addressing
control, and initialization operations.
The MU9C RCP architecture uses direct hardware control
of the device and an independent bus for returning match
results. Software control is also supported for systems
where maximum performance is not needed.
OPERATIONAL OVERVIEW
The MU9C RCP is designed to act as an address translator for
lookup tables in layer 3 switches, routers, and layer 2
switches. Refer to Figure 2 for a simplified block diagram of
a switch. During normal operation, the controller extracts the
address information from an arriving packet to form the
comparand, which is then compared against the contents of
the MU9C RCP. The MU9C RCP generates an index that is
used to access the data in an external RAM, which holds the
destination port for accessing the network. The controller
reads the data from the RAM and forwards the packet.
A unique feature of the MU9C RCP is its ternary comparison
that processes IPv4 CIDR addresses in a single cycle. The
bits of each MU9C RCP word are paired, such that each pair
can contain two binary values (0,1) or one ternary (0,1,X=
"Don't Care") value. A ternary value uses two bits, pairing bit
n from the first 32 bits (31-0) with bit n+32. When storing a
ternary 0 or 1, the value to be stored is written into bit n
(0<=n<=31), and the complement of the value is written to bit
n+32. Thus, a ternary 0 written to ternary pair 7 would consist
of a 0 stored in bit 7 and a 1 stored in bit 39. When storing a
ternary X, 0 is written to both bits in the pair.
Using bit pairs that are 32 bits apart simplifies the
computation of the pair by a processor. Assume that the
ternary value we wish to store is contained in two 32-bit
processor words. Word A contains the value to be stored and
word M contains a mask value, with a 0 in each position at
which an X is to be stored. The value to be written to bits
31-0 of the MU9C RCP is (A&M) and the value to be written
to bits 63-32 of the MU9C RCP is (~A&M).
A special instruction, CMPT DQ, performs the ternary
comparison processing for IPv4 CIDR addresses. The data on
the DQ bus are used directly as both the comparand and
compare mask bits 31-0, and the one's complement of the DQ
bus data are used as both the comparand and compare mask
bits 63-32. As a result, this instruction matches a DQ bit of 0
with bit pairs storing both 0 and X, and a DQ bit of 1 matches
bit pairs storing both 1 and X.
IPv4 CIDR addresses are prioritized by placing their
ternary-encoded values into the MU9C RCP memory such
that entries with longer netmasks (longer matches) have
higher priority (lower indices). Thus, when the MU9C RCP
performs a ternary comparison, it will return the index of the
longest matching entry. Typically, the system is initialized by
a processor that writes routing table information into the
MU9C RCP. The index at which a write takes place is driven
onto the PA:AA bus, so that output port data can be written
simultaneously into the external RAM at the correct index.
The validity of a location in the Address Database is
determined by an extra bit called the Validity bit. This bit is
set and reset either with an index or an associative match.
Therefore, when a new entry is written to the database, its
Validity bit is set valid.
When a database location is deleted, the Validity bit for that
entry is reset, and the index of the location is driven onto the
Active Address bus. This simple mechanism allows easy
maintenance of the tables in both the database and the
external RAM.
The MU9C RCP supports simple daisy chained vertical
cascading that serves to prioritize multiple devices and
provides system-level match and full indication. If the slight
timing overhead associated with the daisy chain is
unacceptable, the MU9C RCP is designed to facilitate
external prioritization across multiple devices.
For layer 2 applications, the MAC addresses are processed in
a binary mode, and the MU9C RCP looks for an exact match.
An MU9C RCP can be used to process both MAC addresses
and IPv4 CIDR in the same device.
2
Rev. 8.10
MU9C Routing CoProcessor (RCP) Family
Packet Stream
C ontroller
Switch C ontrol
And Packet
D ata
RCP
C ontrol
N etwork
Address
D ata
Switch
Fabric
R AM
Address
M U 9C
R AM
Figure 2: Switch Block Diagram
PIN DESCRIPTIONS
Note:
Signal names that start with a slash ("/") are active LOW. All signals are 3.3V CMOS level. Never leave inputs floating. The CAM
architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer to the
Electrical Characteristics section for more information.
DQ31-0 (Data Bus, Three-state, Common
Input/ Output)
The DQ31-0 lines convey data to and from the MU9C
RCP. When the /E input is HIGH the DQ31-0 lines are
held in their high-impedance state. The /W input deter-
mines whether data flows to or from the device on the
DQ31-0 lines. The source or destination of the data is
determined by the AC bus, DSC, and the /AV line. During
a Write cycle, data on the DQ31-0 lines is registered by the
falling edge of /E.
DSC (Data Segment Control, Input)
When DQ bus access to a 64 bit register or memory word
is performed, the DSC input determines whether bits 31-0
(DSC LOW) or bits 63-32 (DSC HIGH) are accessed.
Access to 32 bit registers require that DSC be held LOW.
AA12-0/AA11-0 (Active Address, Output)
The AA bus conveys the Match address, the Next Free
address, or Random Access address, depending on the
most recent memory cycle. The /OE input enables the AA
bus; when the /OE input is HIGH, the AA bus is in its
high-impedance state; when /OE is LOW the AA bus is
active. In a vertically cascaded system after a Comparison
cycle, Write at Next Free Address cycle or Read/Write at
Highest-Priority match, only the highest-priority device
will enable its AA bus, regardless of the state of the /OE
input. In the event of a mismatch in the Address Database
after a Compare cycle, or after a Write at Next Free
Address cycle into an already full system, the lowest-pri-
ority device will drive the AA bus with all 1s. The AA bus
is latched when /E is LOW, and are free to change only
when /E is HIGH.
AC12-0/AC11-0 (Address/Control Bus, Input)
When Hardware control is selected, the AC bus conveys
address or control information to the MU9C RCP, depend-
ing on the state of the /AV input. When /AV is LOW then
the AC bus carries an address; when /AV is HIGH the AC
bus carries control information. Data on the AC bus is reg-
istered by the falling edge of /E. When software control is
selected, the state of the AC bus does not affect the opera-
tion of the device.
Rev. 8.10
3
MU9C Routing CoProcessor (RCP) Family
Pin Descriptions
AA12/NC*
AA11
AA10
VDD
VDD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
VSS
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
DQ14
DQ15
VSS
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
20
1
2
3
4
5
6
7
8
9
51
DSC
VSS
VSS
VSS
VSS
VSS
/MM
PA3
PA2
PA1
PA0
AA9
AA8
AA7
AA6
AA5
AA4
AA3
AA2
AA1
AA0
/MF
/FF
/MI
/FI
50
49
48
47
46
45
44
AC12/NC*
AC11
AC10
AC9
AC8
VSS
AC7
AC6
AC5
AC4
VDD
AC3
AC2
AC1
AC0
VSS
TDO
TDI
TMS
TCLK
MU9CxK64
100-PIN LQFP
(Top View)
43
42
41
40
39
38
37
36
35
34
33
32
31
/CS1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/CS2
/RESET
/TRST
VDD
VDD
/OE
/E
/AV
VSS
VSS
VSS
/VB
/W
* NC on MU9C4K64
Figure 3: MU9C RCP 100-LQFP Pinout
VDDCORE #
AA12*
AA11
AA10
VDD
VDD
DSC
66
VSS
VSS
VSS
VSS
/MM
67
PA3
PA2
PA1
PA0
AA9
AA8
AA7
AA6
AA5
AA4
AA3
AA2
AA1
AA0
/MF
/FF
NC
NC
NC
NC
NC
NC
NC
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
102
101
100
65
NC
/MI
/FI
VSS
VDDCORE #
DQ0
DQ1
DQ2
DQ3
VDDCORE #
VDD
DQ4
DQ5
DQ6
DQ7
VSS
VSS
DQ8
DQ9
DQ10
DQ11
VDDCORE #
VDD
DQ12
DQ13
DQ14
DQ15
VSS
VSS
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
1
2
3
4
5
6
7
8
9
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
NC
NC
NC
NC
NC
NC
AC12*
AC11
AC10
AC9
AC8
VSS
AC7
AC6
AC5
AC4
VDD
VDDCORE #
AC3
AC2
AC1
AC0
VDDCORE #
VSS
TDO
TDI
MU9CxK64
128-PIN LQFP
(Top View)
/CS1
DQ28
DQ29
DQ30
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ16
DQ17
DQ18
DQ19
DQ27
VDDCORE #
DQ31
VDDCORE #
/CS2
VDDCORE #
VDDCORE #
/RESET
/TRST
VDD
VDD
/OE
/E
/AV
/VB
TCLK
TMS
VSS
VSS
VSS
VSS
VSS
/W
Figure 3b: MU9C RCP 128-LQFP Pinout
* NC on MU9C4K64
# See Pin Description
for VDDCORE
4
Rev. 8.10
Pin Descriptions
MU9C Routing CoProcessor (RCP) Family
PA3-0 (Page Address, Output)
The PA3-0 lines convey Page Address information. When
the /OE input is HIGH, the PA3-0 outputs are in their
high-impedance state; when /OE is LOW the PA3-0 lines
carry the Page Address value held in the Configuration
register. The PA3-0 lines are latched when /E is LOW, and
are free to change only when /E is HIGH. The Page
Address value of the currently active or highest-priority
responding device is output at the same time, and under
the same conditions, as the AA bus is active.
/AV (Address Valid, Input)
When Hardware control is selected, the /AV input
determines whether the AC bus carries address or control
information. When /AV is LOW, the AC bus conveys a
memory address; when /AV is HIGH, the AC bus conveys
control information. The state of the /AV line is registered
by the falling edge of /E. When software control is
selected, the /AV line distinguishes between instructions
and data on the DQ31-0 lines; when /AV is LOW, data is
present on the DQ31-0 lines; when /AV is HIGH, an
instruction is present on the DQ11-0 lines.
/E (Chip Enable, Input)
The /E input is the main chip enable and synchronizing
control for the MU9C RCP. When /E is HIGH, the chip is
disabled and the DQ31-0 lines are held in their
high-impedance state. The falling edge of /E registers the
/W, /CS1, /CS2, /AV, /AC bus, DSC, and the /VB and
DQ31-0 lines for a Write cycle. /E being LOW causes the
results of the previous comparison or memory access to be
latched on the PA:AA bus; when /E goes HIGH the latches
opens allowing the new comparison results or random
access memory address to flow to the PA:AA bus.
/VB (Validity
Input/Output)
Bit,
Three-state,
Common
During accesses over the DQ31-0 lines, the /VB line
conveys validity information to and from the MU9C RCP.
During a Write cycle (/W=LOW), when /VB is LOW the
addressed location is set valid; when /VB is HIGH it is set
empty. During a Read cycle (/W=HIGH), the validity of
the addressed location is read on the /VB line. During a
Write cycle, the state of the /VB line is registered by the
falling edge of /E.
/CS1, /CS2 (Chip Select 1, Chip Select 2,
Inputs)
The /CS1 and /CS2 inputs enable the MU9C RCP. If either
/CS1 or /CS2 are LOW, the device is selected for a Read,
Write, or Compare cycle through the DQ31-0 lines, or for
an internal data transfer. The /CS1 and /CS2 lines do not
have any effect on the PA:AA bus. The state of the /CS1
and /CS2 lines is registered by the falling edge of /E.
/MF (Match Flag, Output)
The /MF output indicates whether a valid match has
occurred during the previous Comparison cycle. If the
/MF output is HIGH at the end of a Comparison cycle,
then no match occurred; if it is LOW then either a match
occurred within the device, or the /MI input is LOW,
conditioned by the /MF output from a higher-priority
device in the system. The state of the /MF line will not
change until after the rising edge of /E during the
Comparison cycle. Note that /MF indicates the results of
the most recent Comparison cycle; it will not change when
the PA:AA bus carry an address other than the Match
address.
/W (Write Enable, Input)
The /W input determines the direction of data transfer on
the DQ31-0 lines during Read, Write, and Data Move
cycles. When /W is LOW, data flows into the DQ31-0
lines; when /W is HIGH, data flows out. The /W line also
conditions the control state present on the AC bus and
DSC lines. The state of the /W line is registered by the
falling edge of /E.
/MI (Match Input, Input)
The /MI input receives match information from the next
higher-priority MU9C RCP in a vertically cascaded
system to provide system-level prioritization. When the
/MI input is HIGH, the /MF output will only go LOW if
there is a match during a Comparison cycle; when the /MI
input is LOW, the /MF output will go LOW. The /MF
output from one device is connected to the /MI input of the
next lower-priority device. The /MI pin of the
highest-priority device must be tied HIGH.
/OE (Output Enable, Input)
The /OE input enables the PA:AA bus. When /OE is
HIGH, PA:AA bus are in their high-impedance state.
When /OE is LOW, PA:AA bus are active, and convey the
results of the last Comparison Cycle Match address or
Memory Access address. In a vertically cascaded system,
only the PA:AA bus of the highest-priority device will be
activated by /OE being LOW; in lower-priority devices,
the PA:AA bus remains in high-impedance regardless of
the state of /OE.
Rev. 8.10
5
