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ADVANCED INFORMATION

MX28F640C3T/B

64M-BIT [4M x16] CMOS SINGLE VOLTAGE

3V ONLY FLASH MEMORY

FEATURES

• Bit Organization: 4,194,304 x 16

• Single power supply operation

- 3.0V only operation for read, erase and program

operation

- VCC=VCCQ=2.7~3.6V

- Operating temperature:-40°

C~85°

• Fast access time : 90/120ns

• Low power consumption

- 9mA maximum active read current, f=5MHz (CMOS

input)

- 21mA program erase current maximum

(VPP=1.65~3.6V)

- 7uA typical standby current under power saving

mode

• Sector architecture

- Sector Erase (Sector structure : 4Kword x 2 (boot

sectors), 4Kword x 6 (parameter sectors), 32Kword x

127 (parameter sectors)

- Top/Bottom Boot

• Auto Erase (chip & sector) and Auto Program

- Automatically program and verify data at specified

address

• Automatic Suspend Enhance

- Word write suspend to read

- Sector erase suspend to word write

- Sector erase suspend to read register report

• Automatic sector erase, full chip erase, word write and

sector lock/unlock configuration

• Status Reply

- Detection of program and erase operation comple-

tion.

- Command User Interface (CUI)

- Status Register (SR)

Data Protection Performance

- Include boot sectors and parameter and main sectors

to be block/unblock

100,000 minimum erase/program cycles

Common Flash Interface (CFI)

128-bit Protection Register

- 64-bit Unique Device Identifier

- 64-bit User-Programmable

Latch-up protected to 100mA from -1V to VCC+1V

Package type:

- 48-pin TSOP (12mm x 20mm)

- 48-ball CSP (11mm x 12mm)

•

GENERAL DESCRIPTION

The MX28F640C3T/B is a 64-mega bit Flash memory

organized as 4M words of 16 bits. The 1M word of data

is arranged in eight 4Kword boot and parameter sectors,

and 127 32Kword main sector which are individually

erasable. MXIC's Flash memories offer the most cost-

effective and reliable read/write non-volatile random ac-

cess memory. The MX28F640C3T/B is packaged in 48-

pin TSOP and 48-ball CSP. It is designed to be repro-

grammed and erased in system or in standard EPROM

programmers.

The standard MX28F640C3T/B offers access time as

fast as 90ns, allowing operation of high-speed micropro-

cessors without wait states.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX28F640C3T/B uses a command register to manage

this functionality. The command register allows for 100%

TTL level control inputs and fixed power supply levels

during erase and programming, while maintaining maxi-

mum EPROM compatibility.

MXIC Flash technology reliably stores memory contents

even after 100,000 erase and program cycles. The MXIC

cell is designed to optimize the erase and programming

P/N:PM0900

REV. 0.6, AUG. 20, 2003

MX28F640C3T/B

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields

for erase and program operations produces reliable cy-

cling. The MX28F640C3T/B uses a 2.7V~3.6V VCC sup-

ply to perform the High Reliability Erase and auto Pro-

gram/Erase algorithms.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC + 1V.

The dedicated VPP pin gives complete data protection

when VPP< VPPLK.

A Command User Interface (CUI) serves as the inter-

face between the system processor and internal opera-

tion of the device. A valid command sequence written to

the CUI initiates device automation. An internal Write

State Machine (WSM) automatically executes the algo-

rithms and timings necessary for erase, full chip erase,

word write and sector lock/unlock configuration opera-

tions.

A sector erase operation erases one of the device's 32K-

word sectors typically within 1.0s, 4K-word sectors typi-

cally within 0.5s independent of other sectors. Each sec-

tor can be independently erased minimum 100,000 times.

Sector erase suspend mode allows system software to

suspend sector erase to read or write data from any other

sector.

Writing memory data is performed in word increments of

the device's 32K-word sectors typically within 0.8s and

4K-word sectors typically within 0.1s. Word program sus-

pend mode enables the system to read data or execute

code from any other memory array location.

MX28F640C3T/B features with individual sectors lock-

ing by using a combination of bits thirty-nine sector lock-

bits and WP, to lock and unlock sectors.

The status register indicates when the WSM's sector

erase, full chip erase, word program or lock configura-

tion operation is done.

The access time is 90/120ns (tELQV) over the operat-

ing temperature range (-40° to +80° and VCC supply

voltage range of 2.7V~3.6V.

MX28F640C3T/B's power saving mode feature substan-

tially reduces active current when the device is in static

mode (addresses not switching). In this mode, the typi-

cal ICCS current is 7uA (CMOS) at 3.0V VCC.

As CE and RESET are at VCC, ICC CMOS standby

mode is enabled. When RESET is at GND, the reset

mode is enabled which minimize power consumption and

provide data write protection.

A reset time (tPHQV) is required from RESET switching

high until outputs are valid. Similarly, the device has a

wake time (tPHEL) from RESET-high until writes to the

CUI are recognized. With RESET at GND, the WSM is

reset and the status register is cleared.

P/N:PM0900

REV. 0.6, AUG. 20, 2003

MX28F640C3T/B

BLOCK DIAGRAM

Q0~Q7

Output

Buffer

Input

Buffer

I/O

Logic

VCC

Output

Multiplexer

Identifier

Data

Command

User

Interface

RESET

Status

Data

Comparator

Write

State

Machine

A0~A21

Input

Buffer

Decoder

Y-Gating

Program/Erase

Voltage Switch

VPP

VCC

Main Sector 125

Boot Sector 0

Boot Sector 1

Parameter Sector

Main Sector 126

GND

Main Sector 0

Main Sector 1

Address

Latch

Decoder

32K-Word

Main Sector

x127

.......

Address

Counter

.......

P/N:PM0900

REV. 0.6, AUG. 20, 2003

MX28F640C3T/B

PIN CONFIGURATIONS

48 TSOP (Standard Type) (12mm x 20mm)

A15

A14

A13

A12

A11

A10

A21

A20

RESET

VPP

A19

A18

A17

A16

VCCQ

GND

Q15

Q14

Q13

Q12

VCC

Q11

Q10

GND

MX28F640C3T/B

48 Ball CSP (11 mm x 12 mm) Top View, Ball Down (Ball Pitch=0.75mm, Ball Width=0.35mm)

A13

A14

A15

A16

VCCQ

GND

A11

A10

A12

Q14

Q15

Q13

VPP

RESET

A21

Q11

Q12

A18

A20

VCC

A19

A17

Q10

12 mm

GND

11 mm

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REV. 0.6, AUG. 20, 2003

MX28F640C3T/B

Table 1. Pin Description

Symbol

A0-A21

Type

input

Description and Function

Address inputs for memory address. Data pin float to high-impedance when the chip is

deselected or outputs are disable. Addresses are internally latched during a write or

erase cycle.

Data inputs/outputs: Inputs array data on the second CE and WE cycle during a pro-

gram command. Data is internally latched. Outputs array and configuration data. The

data pin float to tri-state when the chip is de-selected.

Activates the device's control logic, input buffers, and sense amplifiers. CE high de-

selects the memory device and reduce power consumption to standby level. CE is

active low.

Reset Deep Power Down: when RESET=VIL, the device is in reset/deep power down

mode, which drives the outputs to High Z, resets the WSM and minimizes current level.

When RESET=VIH, the device is normal operation. When RESET transition the device

defaults to the read array mode.

Write Enable: to control write to CUI and array sector. WR=VIL becomes active. The

data and address is latched WE on the rising edge of the second WE pulse.

Program/Erase Power Supply:(1.65V~3.6V)

Lower VPP<VPPLK, to protect any contents against Program and Erase Command.

Set VPP=VCC for in-system Read, Program and Erase Operation.

Output enable: gates the device's outputs during a real cycle.

Write protect: when WP is VIL, the boot sectors cannot be written or erased. When WP

is VIH, locked boot sectors cannot be written or erase. WP is not affected parameter

and main sectors.

Device power supply: (2.7V~3.6V).

I/O Power Supply: supplies for input/output buffers.

[2.7V~3.6V] This input should be tied directly to VCC.

Ground voltage: all the GND pin shall not be connected.

Q0-Q15

input/output

input

RESET

input

VPP

input

input/supply

input

VCC

VCCQ

GND

supply

input

supply

P/N:PM0900

REV. 0.6, AUG. 20, 2003