NCP5351
4 A Synchronous Buck
Power MOSFET Driver
The NCP5351 is a dual MOSFET gate driver optimized to drive the
gates of both high−side and low−side Power MOSFETs in a
Synchronous Buck converter. The NCP5351 is an excellent
companion to multiphase controllers that do not have integrated gate
drivers, such as ON Semiconductor’s CS5323, CS5305 or CS5307.
This architecture provides a power supply designer the flexibility to
locate the gate drivers close to the MOSFETs.
The 4.0 A drive capability makes the NCP5351 ideal for minimizing
switching losses in MOSFETs with large input capacitance. Optimized
internal, adaptive nonoverlap circuitry further reduces switching
losses by preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate MOSFET drain
voltages as high as 25 V. Both gate outputs can be driven low, and
supply current reduced to less than 25
mA,
by applying a low logic
level to the Enable (EN) pin. An undervoltage lockout function
ensures that both driver outputs are low when the supply voltage is
low, and a thermal shutdown function provides the IC with
overtemperature protection.
The NCP5351 is pin−to−pin compatible with the SC1205 and is
available in a standard SO−8 package and thermally enhanced
DFN−10.
Features
http://onsemi.com
MARKING
DIAGRAMS
8
8
1
SO−8
D SUFFIX
CASE 751
1
DFN−10
MN SUFFIX
CASE 485C
A
L
Y
W
10
5351
ALYW
1
5351
ALYW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
DRN
TG
BST
CO
DFN−10
1
DRN
TG
N/C
BST
CO
10
GND
BG
N/C
V
S
EN
1
SO−8
8
PGND
BG
V
S
EN
•
•
•
•
•
•
•
•
•
•
•
4.0 A Peak Drive Current
Rise and Fall Times < 15 ns Typical into 6000 pF
Propagation Delay from Inputs to Outputs < 20 ns
Adaptive Nonoverlap Time Optimized for Large Power MOSFETs
Floating Top Driver Accommodates Applications Up to 25 V
Undervoltage Lockout to Prevent Switching when the Input
Voltage is Low
Thermal Shutdown Protection Against Overtemperature
< 1.0 mA Quiescent Current − Enabled
25
mA
Quiescent Current − Disabled
Internal TG to DRN Pulldown Resistor Prevents HV Supply−Induced
Turn On of High−Side MOSFET
Pb−Free Package is Available
ORDERING INFORMATION
Device
NCP5351D
NCP5351DR2
NCP5351MNR2
NCP5351MNR2G
Package
SO−8
SO−8
DFN−10
DFN−10
(Pb−Free)
Shipping
†
98 Units/Rail
2500 Tape & Reel
2500 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2004
1
November, 2004 − Rev. 11
Publication Order Number:
NCP5351/D
NCP5351
BST
V
S
+
−
+
−
4.25 V
Delay
Nonoverlap
Control
Level
Shifter
TG
DRN
EN
Delay
Thermal
Shutdown
V
S
CO
PGND
Figure 1. Block Diagram
Table 1. Input−Output Truth Table
EN
L
H
H
H
H
CO
X
L
H
L
H
DRN
X
< 3.0 V
< 3.0 V
> 5.0 V
> 5.0 V
TG
L
L
H
L
H
BG
L
H
L
L
L
V
CO
tpdl
BG
tpdl
TG
tf
TG
V
TG
−V
DRN
tr
TG
tpdh
TG
(Nonoverlap)
V
BG
tf
BG
tr
BG
tpdh
BG
(Nonoverlap)
V
DRN
4.0 V
Figure 2. Timing Diagram
http://onsemi.com
2
+
−
4.0 V
BG
NCP5351
PACKAGE PIN DESCRIPTION
Pin Number
SO−8
1
2
3
DFN−10
1
2
4
Pin Symbol
DRN
TG
BST
Description
The switching node common to the high and low−side FETs. The high−side (TG) driv-
er and supply (BST) are referenced to this pin.
Driver output to the high−side MOSFET gate.
Bootstrap supply voltage input. In conjunction with a Schottky diode to V
S
, a 0.1
mF
to
1.0
mF
ceramic capacitor connected between BST and DRN develops supply voltage
for the high−side driver (TG).
Logic level control input produces complementary output states − no inversion at TG;
inversion at BG.
Not Connected.
Logic level enable input forces TG and BG low, and supply current to 10
mA
when
EN is low.
Power supply input. A 0.1
mF
to 1.0
mF
ceramic capacitor should be connected from
this pin to PGND.
Driver output to the low−side (synchronous rectifier) MOSFET gate.
Ground.
Ground.
4
−
5
6
7
8
−
5
3, 8
6
7
9
−
10
CO
N/C
EN
V
S
BG
PGND
GND
http://onsemi.com
3
NCP5351
MAXIMUM RATINGS − SO−8
Rating
Operating Junction Temperature, T
J
Package Thermal Resistance: SO−8
Junction−to−Case, R
qJC
Junction−to−Ambient, R
qJA
Storage Temperature Range, T
S
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
Pb−Free
Value
Internally Limited
45
165
−65 to 150
230 peak
260 peak
1
Unit
°C
°C/W
°C/W
°C
°C
−
MSL Rating
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
1. 60 seconds maximum above 183°C.
MAXIMUM RATINGS − DFN−10
Rating
Maximum Voltage All Pins
Maximum Operating Voltage All Pins
Thermal Resistance, Junction−to−Air
Operating Ambient Temperature Range
ESD Withstand Voltage
Moisture Sensitivity
Storage Temperature Range
Junction Operating Temperature
Human Body Model (Note 2)
Machine Model (Note 2)
Symbol
V
max
V
max
R
JA
T
A
V
ESD
MSL
T
stg
T
J
Value
5.5
5.2
68.5
−30 to 85
> 2500
> 150
Level 1
−55 to 150
−30 to 125
°C
°C
Unit
V
V
°C/W
°C
V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
2. This device series contains ESD protection and exceeds the following tests:
Human Body Model, 100 pF discharge through a 1.5 kW following specification JESD22/A114.
Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
Latchup as per JESD78 Class II: > 100 mA.
MAXIMUM RATINGS
Pin Symbol
V
S
BST
DRN
Pin Name
Main Supply Voltage Input
Bootstrap Supply Voltage
Input
Switching Node
(Bootstrap Supply Return)
High−Side Driver Output
(Top Gate)
Low−Side Driver Output
(Bottom Gate)
TG & BG Control Input
Enable Input
Ground
V
MAX
6.3 V
25 V wrt/PGND
6.3 V wrt/DRN
25 V
V
MIN
−0.3 V
−0.3 V wrt/DRN
−1.0 V DC
−5.0 V for 100 ns
−6.0 V for 20 ns
−0.3 V wrt/DRN
−0.3 V
−0.3 V
−0.3 V
0V
I
SOURCE
NA
NA
4.0 A Peak (< 100
ms)
250 mA DC
4.0 A Peak (< 100
ms)
250 mA DC
4.0 A Peak (< 100
ms)
250 mA DC
1.0 mA
1.0 mA
4.0 A Peak (< 100
ms)
250 mA DC
I
SINK
4.0 A Peak (< 100
ms)
250 mA DC
4.0 A Peak (< 100
ms)
250 mA DC
NA
TG
BG
CO
EN
PGND
NOTE:
25 V wrt/PGND
6.3 V wrt/DRN
6.3 V
6.3 V
6.3 V
0V
4.0 A Peak (< 100
ms)
250 mA DC
4.0 A Peak (< 100
ms)
250 mA DC
1.0 mA
1.0 mA
NA
All voltages are with respect to PGND except where noted.
http://onsemi.com
4
NCP5351
ELECTRICAL CHARACTERISTICS
(0°C < T
J
< 125°C; V
S
= 5.0 V; 4.0 V < V
BST
< 25 V; V
EN
= V
S
; unless otherwise noted)
Parameter
DC OPERATING SPECIFICATIONS
POWER SUPPLY
V
S
Quiescent Current, Operating
V
BST
Quiescent Current, Operat-
ing
Quiescent Current, Non−Operat-
ing
Undervoltage Lockout
Start Threshold
Hysteresis
CO INPUT CHARACTERISTICS
High Threshold
Low Threshold
Input Bias Current
EN INPUT CHARACTERISTICS
High Threshold
Low Threshold
Input Bias Current
THERMAL SHUTDOWN
Overtemperature Trip Point
Hysteresis
HIGH−SIDE DRIVER
Peak Output Current
Output Resistance (Sourcing)
Output Resistance (Sinking)
LOW−SIDE DRIVER
Peak Output Current
Output Resistance (Sourcing)
Output Resistance (Sinking)
−
Duty Cycle < 2.0%, Pulse Width < 100
ms,
T
J
= 125°C,
V
S
= 4.5 V, V
BG
= 4.0 V
Duty Cycle < 2.0%, Pulse Width < 100
ms,
T
J
= 125°C,
V
S
= 4.5 V, V
BG
= 0.5 V
−
−
−
4.0
0.6
0.42
−
−
−
A
W
W
−
Duty Cycle < 2.0%, Pulse Width < 100
ms,
T
J
= 125°C,
V
BST
− V
DRN
= 4.5 V, V
TG
= 4.0 V + V
DRN
Duty Cycle < 2.0%, Pulse Width < 100
ms,
T
J
= 125°C, V
BST
− V
DRN
= 4.5 V, V
TG
= 0.5 V + V
DRN
−
−
−
4.0
0.5
0.42
−
−
−
A
W
W
−
−
−
−
170
30
−
−
°C
°C
Both outputs respond to CO
Both outputs are low, independent of CO
0 < V
EN
< V
S
2.0
−
−
−
−
0
−
0.8
10
V
V
mA
0 < V
CO
< V
S
−
−
2.0
−
−
−
−
0
−
0.8
1.0
V
V
mA
CO = 0 V
CO = 0 V
4.05
−
4.25
275
4.48
−
V
mV
V
CO
= 0 V, 4.5 V; No output switching
V
CO
= 0 V, 4.5 V; No output switching
V
EN
= 0 V; V
CO
= 0 V, 4.5 V
−
−
−
1.0
50
−
−
−
25
mA
mA
mA
Test Conditions
Min
Typ
Max
Unit
http://onsemi.com
5
