NCP7662
Inductorless Voltage
Converter
The NCP7662 is a pin–compatible upgrade to the industry standard
TC7660 charge pump voltage converter. It converts a +1.5 V to +15 V
input to a corresponding –1.5 to –15 V output using only two low–cost
capacitors, eliminating inductors and their associated cost, size and
EMI.
The on–board oscillator operates at a nominal frequency of 10 kHz.
Frequency is increased to 35 kHz when pin 1 is connected to V+,
allowing the use of smaller external capacitors. Operation below 10 kHz
(for lower supply current applications) is also possible by connecting an
external capacitor from OSC to ground (with pin 1 open).
The NCP7662 is available in both 8–pin DIP and 8–pin small outline
(SO) packages in commercial and extended temperature ranges.
Features
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MARKING
DIAGRAMS
8
8
1
SO–8
D SUFFIX
CASE 751
1
8
PDIP–8
P SUFFIX
CASE 626
1
YY, Y
WW
X
Z
CO
= Year
= Work Week
= Assembly ID Code
= Subcontractor ID Code
= Country of Orgin
NCP7662
YYWWXZ
CO
NCP
7662
YWWXZ
•
•
•
•
Wide Operating Voltage Range: 1.5 V to 15 V
Boost Pin (Pin 1) for Higher Switching Frequency
High Power Efficiency is 96%
Easy to Use – Requires Only 2 External Non–Critical Passive
Components
•
Improved Direct Replacement for Industry Standard ICL7660 and
Other Second Source Devices
Applications
8
1
CAP+ 2
GND 3
CAP– 4
NCP7662
Package
SO–8
PDIP–8
•
•
•
•
•
Simple Conversion of +5 V to 5 V Supplies
Voltage Multiplication VOUT = nVIN
Negative Supplies for Data Acquisition Systems and Instrumentation
RS232 Power Supplies
Supply Splitter, VOUT = VS/2
"
"
PIN CONNECTIONS
BOOST 1
8 V+
7 OSC
6 LOW
VOLTAGE (LV)
5 VOUT
"
ORDERING INFORMATION
Device
NCP7662DR2
NCP7662P
Shipping
2500 Tape & Reel
50 Units/Rail
©
Semiconductor Components Industries, LLC, 2000
1
June, 2000 – Rev. 0
Publication Order Number:
NCP7662/D
NCP7662
Functional Block Diagram
V+
8
BOOST
1
2
CAP +
7
OSC
6
RC
OSCILLATOR
B
2
VOLTAGE
LEVEL
TRANSLATOR
4
CAP –
LV
5
V OUT
INTERNAL
VOLTAGE
REGULATOR
NCP7662
3
GND
LOGIC
NETWORK
ABSOLUTE MAXIMUM RATINGS
Rating
Supply Voltage
LV, Boost and OSC Inputs Voltage (Note 1.)
V+
5.5 V
5.5 V
Symbol
Value
+16.5
–0.3 V to (V+ + 0.3 V)
+ –5.5 V) to (V+ + 0.3 V)
(V
20
Continuous
µA
V
mW
730
470
–40 to +85
–65 to +150
+300
°C
°C
°C
Unit
V
V
u
t
Current into LV (Note 1.)
V+
3.5 V
u
Output Short Duration
(VSUPPLY
5.5 V)
v
Power Dissipation (Note 2.)
Plastic DIP
SO
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Static–sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses
above those listed under “Absolute Maximum Ratings’’ may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latch–up. It is recommended that no inputs
from sources operating from external supplies be applied prior to “power up’’ of the NCP7662.
2. Derate linearly above 50°C by 5.5 mW/°C.
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NCP7662
ELECTRICAL CHARACTERISTICS
(V+ = 5 V, TA = +25°C, OSC = Free running, Test Circuit Figure 2, unless otherwise specified.)
Characteristics
Supply Current (Note 3.)
(Boost Pin OPEN or GND)
Test Conditions
Symbol
I+
Min
–
–
–
I+
V+H
V+L
ROUT
–
–
3.0
1.5
–
–
–
–
fOSC
PEff
VOUTEff
ZOSC
5.0
–
96
95
99
–
–
Typ
80
–
–
–
–
–
–
65
–
–
–
10
35
96
97
99.9
1.0
100
Max
160
180
180
300
350
15
3.5
100
120
250
300
–
–
–
–
–
–
–
%
MΩ
kΩ
kHz
%
V
V
Ω
µA
Unit
µA
Supply Current
(Boost Pin = V+)
Supply Voltage Range, High (Note 4.)
Supply Voltage Range, Low
Output Source Resistance
v v
v v
0°C
v
TA
v
+70°C
–40°C
v
TA
v
+85°C
RL = 10 kΩ,
LV Open, TMIN
TA
RL = 10 kΩ,
LV to GND, TMIN
TA
RL =
∞,
+25°C
0°C
TA
+70°C
–40°C
TA
+85°C
v v
TMAX
v v
TMAX
IOUT = 20 mA, 0°C
v
TA
v
+70°C
IOUT = 20 mA, –40°C
v
TA
v
+85°C
IOUT = 3 mA, V+ = 2 V, LV to GND,
0°C
TA
+70°C
v v
IOUT = 3 mA, V+ = 2 V, LV to GND,
–40°C
TA
+85°C
v v
Oscillator Frequency
Power Efficiency
COSC = 0, Pin 1 Open or GND
Pin 1 = V+
RL = 5 kΩ,
TMIN
TA
TMAX
v v
RL =
∞
Voltage Conversion Efficiency
Oscillator Impedance
V+ = 2 V
V+ = 5 V
3. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a
very small but finite stray capacitance present, of the order of 5 pF.
4. The NCP7662 can operate without an external diode over the full temperature and voltage range. This device will function in existing designs
which incorporate an external diode with no degradation in overall circuit performance.
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NCP7662
DETAILED DESCRIPTION
The NCP7662 contains all the necessary circuitry to
complete a negative voltage converter, with the exception of
two external capacitors which may be inexpensive 1
µF
polarized electrolytic types. The mode of operation of the
device may be best understood by considering Figure 2,
which shows an idealized negative voltage converter.
Capacitor C1 is charged to a voltage V+ for the half cycle
when switches S1 and S3 are closed. (Note: Switches S2 and
S4 are open during this half cycle.) During the second half
cycle of operation, switches S2 and S4 are closed, with S1
and S3 open, thereby shifting capacitor C1 negatively by V+
volts. Charge is then transferred from C1 to C2 such that the
voltage on C2 is exactly V+, assuming ideal switches and no
load on C2. The NCP7662 approaches this ideal situation
more closely than existing non–mechanical circuits.
In the NCP7662 the four switches of Figure 2 are MOS
power switches; S1 is a P–channel device and S2, S3 and S4
are N–channel devices. The main difficulty with this
approach is that in integrating the switches, the substrates of
S3 and S4 must always remain reverse biased with respect to
their sources, but not so much as to degrade their “ON’’
resistances. In addition, at circuit start up, and under output
short circuit conditions (VOUT = V+), the output voltage
must be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latchup.
The problem is eliminated in the NCP7662 by a logic
network which senses the output voltage (VOUT) together
with the level translators, and switches the substrates of S3
and S4 to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the NCP7662 is an
integral part of the anti–latchup circuitry; however, its
inherent voltage drop can degrade operation at low voltages.
Therefore, to improve low voltage operation, the “LV’’ pin
should be connected to GND, disabling the regulator. For
supply voltages greater than 3.5 volts, the LV terminal must
be left open to insure latchup proof operation and prevent
device damage.
V+
NCP7662
1
2
8
7
6
5
THEORETICAL POWER EFFICIENCY
CONSIDERATIONS
In theory, a voltage converter can approach 100%
efficiency if certain conditions are met:
A. The drive circuitry consumes minimal power.
B. The output switches have extremely low ON resistance
and virtually no offset.
C. The impedances of the pump and reservoir capacitors
are negligible at the pump frequency.
The NCP7662 approaches these conditions for negative
voltage conversion if large values of C1 and C2 are used.
Energy is lost only in the transfer of charge between
capacitors if a change in voltage occurs.
The energy lost
is defined by:
E = 1/2 C1 (V12 – V22)
where V1 and V2 are the voltages on C1 during the pump and
transfer cycles. If the impedances of C1 and C2 are relatively
high at the pump frequency (refer to Figure 2) compared to
the value of RL, there will be a substantial difference in
voltages V1 and V2. Therefore, it is desirable not only to
make C2 as large as possible to eliminate output voltage
ripple, but also to employ a correspondingly large value for
C1 in order to achieve maximum efficiency of operation.
Dos and Don’ts
1. Do not exceed maximum supply voltages.
2. Do not connect the LV terminal to GND for supply
voltages greater than 3.5 volts.
3. Do not short circuit the output to V+ supply for voltages
above 5.5 volts for extended periods; however, transient
conditions including start–up are okay.
4. When using polarized capacitors in the inverting mode,
the + terminal of C1 must be connected to pin 2 of the
NCP7662 and the – terminal of C2 must be connected to
GND.
5. If the voltage supply driving the NCP7662 has a large
source impedance (25–30 ohms), then a 2.2
µF
capacitor
from pin 8 to ground may be required to limit the rate of
rise of the input voltage to less than 2 V/µs.
V IN
S1
S2
IS
V+
(+5 V)
IL
RL
VO
C2
+ 10
µF
C1
10
µF
+
C1
C2
V OUT = – VIN
3
4
S3
S4
Figure 1. Test Circuit
Figure 2. Idealized Negative Voltage Capacitor
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NCP7662
TYPICAL APPLICATIONS
Simple Negative Voltage Converter
R
O
The majority of applications will undoubtedly utilize the
NCP7662 for generation of negative supply voltages.
Figure 3 shows typical connections to provide a negative
supply where a positive supply of +1.5 V to +15 V is
available. Keep in mind that pin 6 (LV) is tied to the supply
negative (GND) for supply voltages below 3.5 volts.
V+
10
µF
+
–
NCP7662
1
2
3
4
8
7
6
5
^
2 23
)
5 103 110 10–6)
)
4 ESRC1
)
ESRC2
R
^
(46
)
20
)
5 ESR )
Ω
O
C
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(fPUMP
C1) term,
rendering an increase in switching frequency or filter
capacitance ineffective. Typical electrolytic capacitors may
have ESRs as high as 10
Ω.
Output Ripple
RO
VOUT = –V+
–
V+
+
(b)
VOUT
10
µF
(a)
–
+
Figure 3. Simple Negative Converter
and its Output Equivalent
The output characteristics of the circuit in Figure 3 can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 3b. The voltage source has a
value of –(V+). The output impedance (RO) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 2), the switching frequency, the value of C1 and C2,
and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for RO is:
R
O
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown
in Figure 4. Segment A is the voltage drop across the ESR
of C2 at the instant it goes from being charged by C1 (current
flowing into C2) to being discharged through the load
(current flowing out of C2). The magnitude of this current
change is 2
IOUT, hence the total drop is 2
IOUT
ESRC2 volts. Segment B is the voltage change across C2
during time t2, the half of the cycle when C2 supplies current
t2/C2 volts. The
to the load. The drop at B is IOUT
peak–to–peak ripple voltage is the sum of these voltage
drops:
V
RIPPLE
^
1
2
f
PUMP
t2
C2
)
ESRC2
I
OUT
^
2(RSW1
)
RSW3
)
ESRC1)
)
2(RSW2
)
RSW4
)
ESRC1)
)
f 1 C
)
ESRC2
PUMP
1
t1
(f
PUMP
+
f
OSC , R
SWX
2
+
MOSFET switch resistance)
1
C1
0
V
–(V+)
B
Combining the four RSWX terms as RSW, we see that:
R
O
^
2
R
SW
)
f
)
ESRC2
Ω
PUMP
)
4
A
ESR
C1
Figure 4. Output Ripple
Paralleling Devices
RSW, the total switch resistance, is a function of supply
voltage and temperature (see the Output Source Resistance
graphs), typically 23
Ω
at +25°C and 5 V. Careful selection
of C1 and C2 will reduce the remaining terms, minimizing
the output impedance. High value capacitors will reduce the
1/(fPUMP C1) component, and low ESR capacitors will
lower the ESR term. Increasing the oscillator frequency will
reduce the 1/(fPUMP
C1) term, but may have the side
effect of a net increase in output impedance when C1
10
µF
and there is not enough time to fully charge the
capacitors every cycle. In a typical application when fOSC =
10 kHz and C = C1 = C2 = 10
µF:
Any number of NCP7662 voltage converters may be
paralleled to reduce output resistance (Figure 5). The
reservoir capacitor, C2, serves all devices, while each device
requires its own pump capacitor, C1. The resultant output
resistance would be approximately:
R
OUT
+
n (number of devices)
OUT
R
(of NCP7662)
u
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