Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
DESCRIPTION
The NE/SE564 is a versatile, high guaranteed frequency
phase-locked loop designed for operation up to 50MHz. As shown
in the Block Diagram, the NE/SE564 consists of a VCO, limiter,
phase comparator, and post detection processor.
PIN CONFIGURATIONS
D, N Packages
V+
LOOP GAIN CONTROL
INPUT TO PHASE COMP
FROM VCO
LOOP FILTER
LOOP FILTER
FM/RF INPUT
BIAS FILTER
GND
1
2
3
4
5
6
7
8
16 TTL OUTPUT
15 HYSTERESIS SET
14 ANALOG OUT
13 FREQ. SET CAP
12 FREQ. SET CAP
11
VCO OUT 2
FEATURES
•
Operation with single 5V supply
•
TTL-compatible inputs and outputs
•
Guaranteed operation to 50MHz
•
External loop gain control
•
Reduced carrier feedthrough
•
No elaborate filtering needed in FSK applications
•
Can be used as a modulator
•
Variable loop gain (externally controlled)
APPLICATIONS
10 V+
9
VCO OUT TTL
TOP VIEW
SR01025
•
High speed modems
•
FSK receivers and transmitters
•
Frequency Synthesizers
ORDERING INFORMATION
DESCRIPTION
16-Pin Plastic Small Outline (SO) Package
16-Pin Plastic Dual In-Line Package (DIP)
16-Pin Plastic Dual In-Line Package (DIP)
Figure 1. Pin Configuration
•
Signal generators
•
Various satcom/TV systems
•
pin configuration
TEMPERATURE RANGE
0 to +70°C
0 to +70°C
-55 to +125°C
ORDER CODE
NE564D
NE564N
SE564N
DWG #
SOT109-1
SOT38-4
SOT38-4
BLOCK DIAGRAM
V
+
4
5
1
14
LIMITER
6
PHASE
COMPARATOR
2
DC
7
3
11
9
VCO
10
12
13
8
AMPLIFIER
RETRIEVER
SCHMITT
TRIGGER
16
POST DETECTION
PROCESSOR
15
SR01026
Figure 2. Block Diagram
1994 Aug 31
1
853-0908 13720
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V+
Supply voltage
Pin 1
Pin 10
Sink Max (Pin 9) and sourcing (Pin 11)
Bias current adjust pin (sinking)
Power dissipation
Operating ambient temperature
NE
SE
T
STG
Storage temperature range
NOTE:
Operation above 5V will require heatsinking of the case.
PARAMETER
RATING
14
6
11
1
600
0 to +70
-55 to +125
-65 to +150
UNITS
V
V
mA
mA
mW
I
OUT
I
BIAS
P
D
T
A
°
C
°
C
°
C
DC AND AC ELECTRICAL CHARACTERISTICS
V
CC
= 5V; T
A
= 0 to 25
°
C; f
O
= 5MHz, I
2
= 400µA; unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
Maximum VCO frequency
TEST CONDITIONS
MIN
C
1
= 0 (stray)
Input > 200mV
RMS
T
A
= 25
°
C
T
A
= 125
°
C
T
A
= -55
°
C
T
A
= 0
o
C
T
A
= 70
°
C
Input > 200mV
RMS
, R
2
= 27Ω
f
O
= 5MHz,
T
A
= -55
°
C to +125
°
C
T
A
= 0 to +70
°
C
= 0 to +70
°
C
f
O
= 5MHz,
T
A
= -55
°
C to +125
°
C
T
A
= 0 to +70
°
C
C
1
= 91pF
R
C
= 100Ω “Internal”
V
CC
= 4.5V to 5.5V
Modulation frequency: 1kHz
f
O
= 5MHz, input deviation:
2%T = 25
°
C
1%T = 25
°
C
1%T = 0
°
C
1%T = -55
°
C
1%T = 70
°
C
1%T = 125
°
C
Deviation: 1% to 8%
Std. condition, 1% to 10% dev.
Std. condition, 30% AM
Modulation frequency: 1kHz
f
O
= 5MHz, input deviation: 1%
V
CC
= 4.5V
V
CC
= 5.5V
V
CC
= 5V I
1
, I
10
V
OUT
= 5V, Pins 16, 9
I
OUT
= 2mA, Pins 16, 9
I
OUT
= 6mA, Pins 16, 9
4
50
40
20
50
SE564
TYP
65
70
30
80
MAX
MIN
45
40
LIMITS
NE564
TYP
60
70
% of f
O
70
40
20
30
500
300
1500
600
800
500
5
3
6
8
3.5
5
3
6.5
8
MHz
% of f
O
PPM/
o
C
20
30
% of f
O
MAX
MHz
UNITS
Lock range
Capture range
VCO frequency drift with
temperature
VCO free-running frequency
VCO frequency change with
supply voltage
Demodulated output voltage
16
8
6
12
28
14
10
16
1
40
35
16
8
28
14
13
15
1
40
35
mV
RMS
mV
RMS
mV
RMS
mV
RMS
mV
RMS
mV
RMS
%
dB
dB
mV
RMS
mV
RMS
60
20
0.6
0.8
mA
µA
V
V
Distortion
S/N
Signal-to-noise ratio
AM rejection
Demodulated output at oper-
ating voltage
I
CC
Supply current
Output
“1” output leakage current
“0” output voltage
7
8
12
14
45
1
0.3
0.4
60
20
0.6
0.8
7
8
12
14
45
1
0.3
0.4
1994 Aug 31
2
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
TYPICAL PERFORMANCE CHARACTERISTICS
Lock Range vs Signal Input
1000
8
6
4
INPUT SIGNAL LEVEL – mV
I
PIN
= 0µA
I
PIN
= 40
0
µ
A
2
VCO Capacitor vs Frequency
10
6
2
10
5
CAPACITANCE pF
10
4
10
3
10
2
10
1
2
100
8
6
4
2
V
CC
5V
f
o
= 5MHz
.1
1
10
10
2
10
3
10
4
10
5
FREQUENCY kHz
10
0.7
0.8
0.9
1.0
1.1
1.2
1.3
NORMALIZED LOCK RANGE
Typical Noirmalized VCO
Frequency as a Function of
Pin 2 Bias Current
NORMALIZED VCO FREQUENCY
Typical Noirmalized VCO
Frequency as a Function of
Pin 2 Bias Current
NORMALIZED VCO FREQUENCY
Typical Noirmalized VCO
Frequency as a Function of
Temperature
NORMALIZED VCO FREQUENCY
1.10
VCO FREQUENCY: 50MHz
1.05
1.01
1.00
0.99
0.98
0.97
0.96
–600µA
FREQUENCY: 50MHz
1.10
1.05
1.00
0.95
0.90
BIAS CURRENT: — 200µA
FREQUENCY: 5MHz
1.00
0.95
0.90
FREQUENCY: 500MHz
BIAS CURRENT: — 200µA
–400
–200
0
+200
–600µA –400
–200
0
+200
+400
–50
–25
25
0
25
50
75
100
125
BIAS CURENT (µA), PIN 2
BIAS CURENT (µA), PIN 2
TEMPERATURE (IN
o
C)
SR01027
Figure 3. Typical Performance Characteristics
1994 Aug 31
3
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
V
D
– PHASE COMPARATOR’S
OUTPUT VOLTAGE IN mV
800
VCO FREQUENCY
IN MHz
1.6
I
BIAS = 800
µ
A
I
BIAS = 00
µ
A
f
o
= 1.0MHz
200
1.4
I
BIAS
= 200µA
600
I
BIAS
= 400µA
I
BIAS
= 800µA
400
I
BIAS
= 0µA
1.2
0
40
60
100
120
140
160
0 – PHASE
ERROR IN
DEGREES
–400
–200
200
400
600
800
V
D
IN mV
–200
.8
–400
.6
–600
–800
Variation of the Comparator’s Output Voltage
vs Phase Error and Bias Current (K
D
)
VCO Output Frequency as a Function of
Input Voltage and Bias Current (K
O
)
SR01028
Figure 4. Typical Performance Characteristics (cont.)
TEST CIRCUIT
+5V
R3
R1
1K
INPUT
C3
6
0.1µF
1K
7
C2
430pF
C2
430pF
R2
5
R2
4
1
2
10
16
9
3
15
pF
390
VCO
OUYPUT
DEMODULATED
OUTPUT
0.1µF
14
564
13
C1
12
8
SR01029
Figure 5. Test Circuit
1994 Aug 31
4
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
FUNCTIONAL DESCRIPTION
(Figure 6)
The NE564 is a monolithic phase-locked loop with a post detection
processor. The use of Schottky clamped transistors and optimized
device geometries extends the frequency of operation to greater
than 50MHz.
In addition to the classical PLL applications, the NE564 can be used
as a modulator with a controllable frequency deviation.
The output of the PLL can be written as shown in the following
equation:
V
O
=
(f
IN
- f
O
)
K
VCO
(1)
Phase Comparator Section
The phase detection processor consists of a doubled-balanced
modulator with a limiter amplifier to improve AM rejection.
Schottky-clamped vertical PNPs are used to obtain TTL level inputs.
The loop gain can be varied by changing the current in Q
4
and Q
15
which effectively changes the gain of the differential amplifiers. This
can be accomplished by introducing a current at Pin 2.
Post Detection Processor Section
The post detection processor consists of a unity gain
transconductance amplifier and comparator. The amplifier can be
used as a DC retriever for demodulation of FSK signals, and as a
post detection filter for linear FM demodulation. The comparator has
adjustable hysteresis so that phase jitter in the output signal can be
eliminated.
As shown in the equivalent schematic, the DC retriever is formed by
the transconductance amplifier Q
42
- Q
43
together with an external
capacitor which is connected at the amplifier output (Pin 14). This
forms an integrator whose output voltage is shown in the following
equation:
V
O
=
g
M
C
2
V
IN
dt
(3)
K
VCO
= conversion gain of the VCO
f
IN
= frequency of the input signal
f
O
= free-running frequency of the VCO
The process of recovering FSK signals involves the conversion of
the PLL output into logic compatible signals. For high data rates, a
considerable amount of carrier will be present at the output of the
PLL due to the wideband nature of the loop filter. To avoid the use
of complicated filters, a comparator with hysteresis or Schmitt trigger
is required. With the conversion gain of the VCO fixed, the output
voltage as given by Equation 1 varies according to the frequency
deviation of f
IN
from f
O
. Since this differs from system to system, it
is necessary that the hysteresis of the Schmitt trigger be capable of
being changed, so that it can be optimized for a particular system.
This is accomplished in the 564 by varying the voltage at Pin 15
which results in a change of the hysteresis of the Schmitt trigger.
For FSK signals, an important factor to be considered is the drift in
the free-running frequency of the VCO itself. If this changes due to
temperature, according to Equation 1 it will lead to a change in the
DC levels of the PLL output, and consequently to errors in the digital
output signal. This is especially true for narrowband signals where
the deviation in f
IN
itself may be less than the change in f
O
due to
temperature. This effect can be eliminated if the DC or average
value of the signal is retrieved and used as the reference to the
comparator. In this manner, variations in the DC levels of the PLL
output do not affect the FSK output.
g
M
= transconductance of the amplifier
C
2
= capacitor at the output (Pin 14)
V
IN
= signal voltage at amplifier input
With proper selection of C
2
, the integrator time constant can be
varied so that the output voltage is the DC or average value of the
input signal for use in FSK, or as a post detection filter in linear
demodulation.
The comparator with hysteresis is made up of Q
49
- Q
50
with
positive feedback being provided by Q
47
- Q
48
. The hysteresis is
varied by changing the current in Q
52
with a resulting variation in the
loop gain of the comparator. This method of hysteresis control,
which is a DC control, provides symmetric variation around the
nominal value.
Design Formula
The free-running frequency of the VCO is shown by the following
equation:
f
O
≅
1
22 R
C
(C
1
+ C
S
)
(4)
VCO Section
Due to its inherent high-frequency performance, an emitter-coupled
oscillator is used in the VCO. In the circuit, shown in the equivalent
schematic, transistors Q21 and Q23 with current sources Q25 - Q26
form the basic oscillator. The approximate free-running frequency of
the oscillator is shown in the following equation:
1
f
O
≅
22 R
C
(C
1
+ C
S
)
R
C
= R
19
= R
20
= 100Ω (INTERNAL)
C
1
= external frequency setting capacitor
C
S
= stray capacitance
Variation of V
D
(phase detector output voltage) changes the
frequency of the oscillator. As indicated by Equation 2, the
frequency of the oscillator has a negative temperature coefficient
due to the monolithic resistor. To compensate for this, a current I
R
with negative temperature coefficient is introduced to achieve a low
frequency drift with temperature.
(2)
R
C
= 100Ω
C
1
= external cap in farads
C
S
= stray capacitance
The loop filter diagram shown is explained by the following equation:
f
S
=
1
(First Order)
1 + sRC
3
(5)
R = R
12
= R
13
= 1.3kΩ (Internal)*
By adding capacitors to Pins 4 and 5, a pole is added to the loop
transfer at
ω
=
1
RC
3
NOTE:
*Refer to Figure 6.
1994 Aug 31
5
