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NTP13N10
Preferred Device
Power MOSFET
13 A, 100 V, N−Channel
Enhancement−Mode TO−220
Features
•
Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
•
Avalanche Energy Specified
•
I
DSS
and R
DS(on)
Specified at Elevated Temperature
•
Pb−Free Package is Available
Typical Applications
V
DSS
100 V
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R
DS(ON)
TYP
165 mΩ @ 10 V
N−Channel
D
I
D
MAX
13 A
•
PWM Motor Controls
•
Power Supplies
•
Converters
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Source Voltage (R
GS
= 1.0 MΩ)
Gate−to−Source Voltage
−
Continuous
−
Non−Repetitive (t
p
v10
ms)
Drain Current
−
Continuous @ T
A
25°C
−
Continuous @ T
A
100°C
−
Pulsed (Note 1)
Total Power Dissipation @ T
A
= 25°C
Derate above 25°C
Operating and Storage Temperature Range
Single Drain−to−Source Avalanche Energy
−
Starting T
J
= 25°C
(V
DD
= 50 Vdc, V
GS
= 10 Vdc,
I
L
(pk) = 13 A, L = 1.0 mH, R
G
= 25
Ω)
Thermal Resistance
−
Junction−to−Case
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
Value
100
100
"20
"30
Adc
13
8.0
39
64.7
0.43
−55
to
+175
W
W/°C
°C
mJ
85
°C/W
°C
13N10
A
Y
WW
1
2
3
4
Unit
Vdc
Vdc
Vdc
G
S
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
I
DM
P
D
T
J
, T
stg
E
AS
TO−220AB
CASE 221A
STYLE 5
1
Gate
13N10
AYWW
3
Source
2
Drain
R
θJC
T
L
2.32
260
= Device Code
= Assembly Location
= Year
= Work Week
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Pulse Test: Pulse Width = 10
ms,
Duty Cycle = 2%.
ORDERING INFORMATION
Device
NTP13N10
NTP13N10G
Package
TO−220AB
TO−220AB
(Pb−Free)
Shipping
†
50 Units/Rail
50 Units/Rail
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 6
1
Publication Order Number:
NTP13N10/D
NTP13N10
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Collector Current
(V
GS
= 0 Vdc, V
DS
= 100 Vdc, T
J
= 25°C)
(V
GS
= 0 Vdc, V
DS
= 100 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0)
ON CHARACTERISTICS
Gate Threshold Voltage
V
DS
= V
GS,
I
D
= 250
mAdc)
Temperature Coefficient (Negative)
Static Drain−to−Source On−State Resistance
(V
GS
= 10 Vdc, I
D
= 6.5 Adc)
(V
GS
= 10 Vdc, I
D
= 6.5 Adc, T
J
= 125°C)
Drain−to−Source On−Voltage
(V
GS
= 10 Vdc, I
D
= 13 Adc)
Forward Transconductance (V
DS
= 15 Vdc, I
D
= 6.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
(Notes 2 & 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 80 Vdc, I
D
= 13 Adc,
V
GS
= 10 Vdc)
BODY−DRAIN DIODE RATINGS
(Note 2)
Forward On−Voltage
Reverse Recovery Time
(I
S
= 13 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/ms)
Reverse Recovery Stored Charge
2. Pulse Test: Pulse Width = 300
ms
max, Duty Cycle = 2%.
3. Switching characteristics are independent of operating junction temperature.
(I
S
= 13 Adc, V
GS
= 0 Vdc)
(I
S
= 13 Adc, V
GS
= 0 Vdc, T
J
= 125°C)
V
SD
t
rr
t
a
t
b
Q
RR
−
−
−
−
−
−
0.98
0.88
85
60
28
0.3
1.3
−
−
−
−
−
mC
Vdc
ns
(V
DD
= 80 Vdc, I
D
= 13 Adc,
V
GS
= 10 Vdc, R
G
= 9.1
Ω)
t
d(on)
t
r
t
d(off)
t
f
Q
tot
Q
gs
Q
gd
−
−
−
−
−
−
−
11
40
20
36
14
3.0
7.0
20
80
40
70
20
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
390
115
35
550
160
70
pF
V
GS(th)
Vdc
2.0
−
−
−
−
−
3.2
−7.6
0.130
0.250
1.82
6.0
4.0
−
0.165
0.400
2.34
−
mhos
mV/°C
Ω
V
(BR)DSS
Vdc
100
−
−
−
−
−
147
−
−
−
−
−
5.0
50
±
100
mV/°C
mAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
R
DS(on)
V
DS(on)
g
FS
Vdc
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2
NTP13N10
26
24
22
20
18
16
14
12
10
8
6
4
2
0
V
GS
= 10 V
9V
8V
7.5 V
6V
5.5 V
5V
4.5 V
0
8
9
1
2
3
4
5
6
7
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10
7V
6.5 V
T
J
= 25°C
I
D
, DRAIN CURRENT (AMPS)
26
24
22
20
18
16
14
12
10
8
6
4
2
0
V
DS
≥
10 V
I
D
, DRAIN CURRENT (AMPS)
T
J
= 25°C
T
J
= 100°C
0
T
J
=
−55°C
10
1
2
3
4
5
6
7
8
9
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
Figure 2. Transfer Characteristics
0.5
0.4
0.3
0.2
0.1
0
V
GS
= 10 V
0.2
T
J
= 25°C
0.175
T
J
= 100°C
0.15
V
GS
= 10 V
V
GS
= 15 V
T
J
= 25°C
T
J
=
−55°C
0.125
0
2
4
6 8 10 12 14 16 18 20 22 24
I
D
, DRAIN CURRENT (AMPS)
26
0.1
0
2
4
6 8 10 12 14 16 18 20 22 24 26
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
R
DS(on),
DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
3
2.5
2
1.5
1
0.5
0
−50 −25
0
25
50
75 100 125 150
T
J
, JUNCTION TEMPERATURE (°C)
175
I
D
= 6.5 A
V
GS
= 10 V
10,000
V
GS
= 0 V
I
DSS
, LEAKAGE (nA)
1000
T
J
= 150°C
100
T
J
= 100°C
10
20
30
60
70
80
90 100
40
50
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTP13N10
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
1000
800
600
C
rss
400
200
0
10
C
rss
5
V
GS
0
V
DS
5
10
15
20
25
C
iss
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
V
DS
= 0 V
C
iss
V
GS
= 0 V
T
J
= 25°C
C, CAPACITANCE (pF)
C
oss
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
Figure 7. Capacitance Variation
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