Data Sheet
December 2002
ORCA
®
Series 3C and 3T
Field-Programmable Gate Arrays
Features
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High-performance, cost-effective, 0.35 µm (OR3C) and
0.3 µm (OR3T) 4-level metal technology, (4- or 5-input
look-up table delay of 1.1 ns with -7 speed grade in
0.3 µm).
Same basic architecture as lower-voltage, advanced
process technology Series 3 architectures. (See
ORCA
Series 3L FPGA documentation.)
Up to 186,000 usable gates.
Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to
allow interconnection to both 3.3 V and 5 V devices,
selectable on a per-pin basis.)
Pin selectable I/O clamping diodes provide 5 V or 3.3 V
PCI compliance and 5 V tolerance on OR3Txxx devices.
Twin-quad programmable function unit (PFU) architec-
ture with eight 16-bit look-up tables (LUTs) per PFU,
organized in two nibbles for use in nibble- or byte-wide
functions. Allows for mixed arithmetic and logic functions
in a single PFU.
Nine user registers per PFU, one following each LUT,
plus one extra. All have programmable clock enable and
local set/reset, plus a global set/reset that can be dis-
abled per PFU.
Flexible input structure (FINS) of the PFUs provides a
routability enhancement for LUTs with shared inputs and
the logic flexibility of LUTs with independent inputs.
Fast-carry logic and routing to adjacent PFUs for nibble-,
byte-wide, or longer arithmetic functions, with the option
to register the PFU carry-out.
Softwired LUTs (SWL) allow fast cascading of up to
three levels of LUT logic in a single PFU for up to 40%
speed improvement.
Supplemental logic and interconnect cell (SLIC) pro-
vides 3-statable buffers, up to 10-bit decoder, and
PAL*-
like AND-OR with optional INVERT in each programma-
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ble logic cell (PLC), with over 50% speed improvement
typical.
Abundant hierarchical routing resources based on rout-
ing two data nibbles and two control lines per set provide
for faster place and route implementations and less rout-
ing delay.
TTL or CMOS input levels programmable per pin for the
OR3Cxx (5.0 V) devices.
Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source.
Built-in boundary scan (
IEEE
†
1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
Enhanced system clock routing for low skew, high-speed
clocks originating on-chip or at any I/O.
Up to four ExpressCLK inputs allow extremely fast clock-
ing of signals on- and off-chip plus access to internal
general clock routing.
StopCLK feature to glitchlessly stop/start ExpressCLKs
independently by user command.
Programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF) latch
for reduced input setup time and zero hold time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and
PAL
-like
functions.
— Output FF and two-signal function generator to
reduce CLK to output propagation delay.
— Fast open-drain dive capability
— Capability to register 3-state enable signal.
Baseline FPGA family used in Series 3+ FPSCs (field
programmable system chips) which combine FPGA logic
and standard cell logic on one device.
■
*
PAL
is a trademark of Advanced Micro Devices, Inc.
†
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1.
ORCA
Series 3 (3C and 3T) FPGAs
Device
OR3T20
OR3T30
OR3T55
OR3C/3T80
OR3T125
System
Gates
‡
36K
48K
80K
116K
186K
LUTs
1152
1568
2592
3872
6272
Registers
1872
2436
3780
5412
8400
Max User RAM
18K
25K
42K
62K
100K
User I/Os
196
228
292
356
452
Array Size
12 x 12
14 x 14
18 x 18
22 x 22
28 x 28
Process
Technology
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
‡ The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.
ORCA
Series 3C and 3T FPGAs
Data Sheet
December 2002
Table of Contents
Contents
Page
Contents
Page
Features.......................................................................1
System-Level Features ................................................4
Description ..................................................................5
FPGA Overview ..........................................................5
PLC Logic ...................................................................5
PIC Logic ....................................................................6
System Features .........................................................6
Routing .......................................................................6
Configuration ..............................................................6
ORCA
Foundry
Development System .....................7
Architecture .................................................................7
Programmable Logic Cells..........................................9
Programmable Function Unit ......................................9
Look-Up Table Operating Modes .............................11
Supplemental Logic and Interconnect Cell (SLIC) 19
PLC Latches/Flip-Flops ............................................23
PLC Routing Resources ...........................................25
PLC Architectural Description ..................................32
Programmable Input/Output Cells.............................34
5 V Tolerant I/O .........................................................35
PCI Compliant I/O .....................................................35
Inputs ........................................................................36
Outputs .....................................................................39
PIC Routing Resources ............................................42
PIC Architectural Description ...................................43
High-Level Routing Resources..................................45
Interquad Routing .....................................................45
Programmable Corner Cell Routing .........................46
PIC Interquad (MID) Routing ....................................47
Clock Distribution Network ........................................48
PFU Clock Sources ..................................................48
Clock Distribution in the PLC Array ..........................49
Clock Sources to the PLC Array ...............................50
Clocks in the PICs ....................................................50
ExpressCLK Inputs ...................................................51
Selecting Clock Input Pins .......................................51
Special Function Blocks ............................................52
Single Function Blocks .............................................52
Boundary Scan .........................................................55
Microprocessor Interface (MPI).................................62
PowerPC System ......................................................63
i960 System ..............................................................64
MPI
Interface to FPGA .............................................65
MPI Setup and Control .............................................66
Programmable Clock Manager (PCM) ......................70
PCM Registers ..........................................................71
Delay-Locked Loop (DLL) Mode ..............................73
Phase-Locked Loop (PLL) Mode .............................74
PCM/FPGA Internal Interface ...................................77
PCM Operation .........................................................77
PCM Detailed Programming .....................................78
PCM Applications .....................................................81
2
PCM Cautions .......................................................... 82
FPGA States of Operation ........................................ 83
Initialization .............................................................. 83
Configuration ........................................................... 84
Start-Up ................................................................... 85
Reconfiguration ....................................................... 86
Partial Reconfiguration ............................................ 86
Other Configuration Options ................................... 86
Using
ORCA
Foundry to Generate
Configuration RAM Data ....................................... 87
Configuration Data Frame ....................................... 87
Bit Stream Error Checking ....................................... 89
FPGA Configuration Modes...................................... 90
Master Parallel Mode ............................................... 90
Master Serial Mode ................................................... 1
Asynchronous Peripheral Mode .............................. 92
Microprocessor Interface
(MPI)
Mode ................... 92
Slave Serial Mode .................................................... 95
Slave Parallel Mode ................................................. 95
Daisy-Chaining ........................................................ 96
Daisy-Chaining with Boundary Scan ....................... 97
Absolute Maximum Ratings...................................... 98
Recommended Operating Conditions .................... 98
Electrical Characteristics.......................................... 99
Timing Characteristics............................................ 101
Description ............................................................ 101
PFU Timing ........................................................... 102
PLC Timing ............................................................ 109
SLIC Timing ........................................................... 109
PIO Timing ............................................................. 110
Special Function Blocks Timing ............................ 113
Clock Timing .......................................................... 121
Configuration Timing ............................................. 131
Readback Timing .................................................. 140
Input/Output Buffer Measurement Conditions........ 141
Output Buffer Characteristics................................. 142
OR3Cxx ................................................................. 142
OR3Txxx ................................................................ 143
Estimating Power Dissipation ................................. 144
OR3Cxx ................................................................. 144
OR3Txxx (Preliminary Information) ........................ 145
Pin Information........................................................ 147
Pin Descriptions .................................................... 147
Package Compatibility .......................................... 151
Compatibility with OR2C/TxxA Series ................... 152
Package Thermal Characteristics .......................... 195
FPGA Maximum Junction Temperature ................ 196
Package Coplanarity .............................................. 197
Package Parasitics................................................. 197
Package Outline Diagrams .................................... 198
Terms and Definitions ............................................ 198
144-Pin TQFP ........................................................ 199
Lattice Semiconductor
Data Sheet
December 2002
ORCA
Series 3C and 3T FPGAs
Table of Contents
Contents
Page
Contents
Page
208-Pin SQFP .........................................................200
208-Pin SQFP2 .......................................................201
240-Pin SQFP .........................................................202
240-Pin SQFP2 .......................................................203
256-Pin PBGA .........................................................204
352-Pin PBGA .........................................................205
432-Pin EBGA .........................................................206
600-Pin EBGA .........................................................207
Ordering Information ...............................................208
Lattice Semiconductor
3
ORCA
Series 3C and 3T FPGAs
Data Sheet
December 2002
phase and duty cycle for input clock rates from
5 MHz to 120 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as dig-
ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers or clock doublers. Two
PCMs are provided per device.
■
System-Level Features
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the
ORCA
Series 3 include:
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Full PCI local bus compliance.
Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to
i960
* and
PowerPC
†
processors with user-configurable
address space provided.
Parallel readback of configuration data capability with
the built-in microprocessor interface.
Programmable clock manager (PCM) adjusts clock
True, internal, 3-state, bidirectional buses with simple
control provided by the SLIC.
32 x 4 RAM per PFU, configurable as single- or dual-
port at >176 MHz. Create large, fast RAM/ROM
blocks (128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
■
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*
i960
is a registered trademark of Intel Corporation.
†
PowerPC
is a registered trademark of International Business
Machines Corporation.
Table 2.
ORCA
Series 3 System Performance
Parameter
16-bit Loadable Up/Down Counter
16-bit Accumulator
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined
1
ROM Mode, Unpipelined
2
Multiplier Mode, Pipelined
3
32 x 16 RAM (synchronous):
Single-port, 3-state Bus
4
Dual-port
5
128 x 8 RAM (synchronous):
Single-port, 3-state Bus
4
Dual-port
5
8-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs
6
32-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs
7
36-bit Parity Check (internal)
# PFUs
2
2
11.5
8
15
4
4
8
8
0.25
0
2
0
2
-4
78
78
19
51
76
97
127
88
88
4.87
2.35
16.06
6.91
16.06
Speed
-5
-6
102
102
25
66
104
127
166
116
116
3.66
1.82
12.07
5.41
12.07
131
131
30
80
127
151
203
139
139
2.58
1.23
9.01
4.21
9.01
-7
168
168
38
102
166
192
253
176
176
2.03
0.99
7.03
3.37
7.03
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers).
4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
4
Lattice Semiconductor
Data Sheet
December 2002
ORCA
Series 3C and 3T FPGAs
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit)
look-up tables (LUTs), eight latches/flip-flops (FFs),
and one additional flip-flop that may be used indepen-
dently or with arithmetic functions.
The PFU is organized in a twin-quad fashion: two sets
of four LUTs and FFs that can be controlled indepen-
dently. LUTs may also be combined for use in arith-
metic functions using fast-carry chain logic in either
4-bit or 8-bit modes. The carry-out of either mode may
be registered in the ninth FF for pipelining. Each PFU
may also be configured as a synchronous 32 x 4 sin-
gle- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from
invertible PFU inputs, or they can be tied high or tied
low. The FFs also have programmable clock polarity,
clock enables, and local set/reset.
The SLIC is connected to PLC routing resources and to
the outputs of the PFU. It contains 3-state, bidirectional
buffers and logic to perform up to a 10-bit AND function
for decoding, or an AND-OR with optional INVERT
(AOI) to perform
PAL
-like functions. The 3-state drivers
in the SLIC and their direct connections to the PFU out-
puts make fast, true 3-state buses possible within the
FPGA, reducing required routing and allowing for real-
world system performance.
Description
FPGA Overview
The
ORCA
Series 3 FPGAs are a new generation of
SRAM-based FPGAs built on the successful OR2C/
TxxA FPGA Series, with enhancements and innova-
tions geared toward today’s high-speed designs and
tomorrow’s systems on a single chip. Designed from
the start to be synthesis friendly and to reduce place
and route times while maintaining the complete
routability of the
ORCA
2C/2T devices, Series 3 more
than doubles the logic available in each logic block and
incorporates system-level features that can further
reduce logic requirements and increase system speed.
ORCA
Series 3 devices contain many new patented
enhancements and are offered in a variety of pack-
ages, speed grades, and temperature ranges.
The
ORCA
Series 3 FPGAs consist of three basic ele-
ments: programmable logic cells (PLCs), programma-
ble input/output cells (PICs), and system-level features.
An array of PLCs is surrounded by PICs. Each PLC
contains a programmable function unit (PFU), a sup-
plemental logic and interconnect cell (SLIC), local rout-
ing resources, and configuration RAM. Most of the
FPGA logic is performed in the PFU, but decoders,
PAL
-like functions, and 3-state buffering can be per-
formed in the SLIC. The PICs provide device inputs and
outputs and can be used to register signals and to per-
form input demultiplexing, output multiplexing, and
other functions on two output signals. Some of the sys-
tem-level functions include the new microprocessor
interface (MPI) and the programmable clock manager
(PCM).
Lattice Semiconductor
5
