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P2781/82/84

General Purpose EMI

Reduction IC

Features

•

Provides up to 15dB of EMI suppression

•

FCC approved method of EMI attenuation

•

Generates a 1X, 2X, and 4X low EMI spread spectrum

clock of the input frequency

•

Input frequency range from 3 to 78MHz

•

External loop filter for spread % adjustment

•

Spreading ranges from ±0.25% to ±5.0%

•

Ultra low cycle-to-cycle jitter

•

Zero-cycle slip

•

3.3V operating voltage range

•

Ultra-low power CMOS design

•

P278xA is available in an 8 pin SOIC Package

source, which provides system wide reduction of EMI of all

clock dependent signals. The P278xA allows significant

system cost savings by reducing the number of circuit

board layers and shielding that are traditionally required to

pass EMI regulations.

The P278xA uses the most efficient and optimized

modulation profile approved by the FCC. The P278xA

modulates the output of a single PLL in order to “spread”

the bandwidth of a synthesized clock and, more

importantly, decreases the peak amplitudes of its

harmonics. This result in significantly lower system EMI

compared to the typical narrow band signal produced by

oscillators and most frequency generators. Lowering EMI

by increasing a signal’s bandwidth is called spread

spectrum clock generation.

Product Description

The P278xA is a versatile spread spectrum frequency

modulator designed specifically for digital camera and other

digital video and imaging applications. The P278xA

reduces electromagnetic interference (EMI) at the clock

Applications

The P278xA is targeted towards MFP, xDSL, fax modem,

set-top box, USB controller, DSC, and embedded systems.

Block Diagram

FS0

FS1

VDD

PLL

Modulation

XIN / CLKIN

XOUT

Crystal

Oscillator

Frequency

Divider

Feedback

Divider

Phase

Detector

VCO

Output

Divider

ModOUT

VSS

NOVEMBER 2010 – Rev. 2.1

Publication Order Number:

P2781/82/84

P2781/82/84

Pin Configuration

XIN / CLKIN

XOUT

FS1

VDD

FS0

P278xA

ModOUT

VSS

Standard pin Configuration offered in both

8 pin SOIC Packages.

Pin Description (P278xA)

Pin#

Pin Name

XIN/CLKIN

XOUT

FS1

VSS

ModOUT

FS0

VDD

Type

Description

Connect to crystal or clock input. This pin has dual functions. It can be connected

either to an external crystal or an external reference clock.

Crystal connection. If using an external reference, this pin must be left

unconnected.

Digital logic input used to select input frequency range (see the

Input Frequency

Selection Table).

This pin has an internal pull-up resistor.

External Loop Filter for the PLL. By changing the value of the CRC circuit, the

percentage spread can be adjusted accordingly. See the

Loop Filter Selection

Table

for detail value.

Ground Connection. Connect to system ground.

Spread Spectrum Clock Output.

Digital logic input used to select input frequency range (see the

Input Frequency

Selection Table).

This pin has an internal pull-up resistor.

Connect to +3.3 V

Input Frequency Selection Table

FS1

FS0

Input (MHz)

3 to 9

10 to 19

20 to 38

39 to 78

Output Frequency Scaling (MHz)

P2781A

3 to 9

10 to 19

20 to 38

39 to 78

P2782A

6 to 18

20 to 38

40 to 76

78 to 156

P2784A

12 to 36

40 to 76

80 to 152

156 to 312

Modulation Rate (KHz)

Fin / 128

Fin / 256

Fin / 512

Fin / 1024

Rev. 2 | Page 2 of 8 | www.onsemi.com

P2781/82/84

Loop Filter Selection Table VDD 3.3V

Contact ON Semiconductor for loop values that are not listed in the table and for

Component selection values for industrial and automotive temperatures.

Input

MHz

21-22

23-24

25-26

27-28

29-30

31-32

33-34

35-36

37-38

39-42

43-46

47-50

51-54

55-58

59-62

63-66

67-70

71-74

75-78

BW = ±0.50%

FS1 FS0

(pF)

270

(pF)

330,000

100,000

(ohm)

220

270

390

510

620

820

1,000

330

390

510

560

620

750

820

910

1,000

1,200

330

390

510

560

620

750

820

910

1,000

1,200

330

390

510

560

620

750

820

910

1,000

1,200

BW = ±0.75%

(pF)

270

(pF)

330,000

100,000

(ohm)

300

390

560

750

1,000

1,200

1,500

510

560

750

820

1,000

1,100

1,200

1,300

1,500

1,600

560

620

750

820

1,000

1,100

1,200

1,300

1,500

1,600

560

620

750

820

1,000

1,100

1,200

1,300

1,600

1,800

(pF)

270

BW = ±1.00%

(pF)

(ohm)

(pF)

560

680

330

680

270

560

680

470

330

680

390

270

560

680

470

330

680

390

270

560

680

470

330

680

390

270

BW = ±1.25%

(pF)

100,000

6,800

3,300

6,800

2,700

100,000

6,800

4,700

3,300

6,800

3,900

2,700

100,000

6,800

4,700

3,300

6,800

3,900

2,700

100,000

6,800

4,700

3,300

6,800

3,900

2,700

(ohm)

510

680

910

1,200

2,200

910

1,100

1,200

1,500

2,200

2,700

910

1,100

1,200

1,500

2,200

2,700

910

1,100

1,200

1,500

2,200

2,700

Note: 1. The BW value is representative of typical conditions.

100,000

390

100,000

560

100,000

750

10,000

1,000

5,600

1,200

12,000

2,200

5,600

2,200

100,000

750

100,000 866(1%)

10,000

1,000

12,000

1,200

5,600

1,200

3,900

1,200

12,000

2,200

10,000

2,200

5,600

2,200

3,300

2,200

100,000

750

100,000 866 (1%)

10,000

1,000

12,000

1,200

6,800

1,200

3,900

1,200

12,000

2,200

10,000

2,200

5,600

2,200

3,300

2,200

100,000

750

100,000 866 (1%)

10,000

1,000

12,000

1,200

6,800

1,200

3,900

1,200

12,000

2,200

8,200

2,200

5,600

2,200

3,300

2,200

Rev. 2 | Page 3 of 8 | www.onsemi.com

P2781/82/84

The P278xA performs Zero Cycle Slip when set at low percentage spreading. This allows no occurrence of system timing

error. The optimal setting should minimize system EMI to the fullest without affecting system performance. The spreading is

described as a percentage deviation of the center frequency.

(Note: the center frequency is the frequency of the external reference input on CLKIN, Pin 1.)

Spread Spectrum Selection

The P2781A is designed for PC peripheral, networking, notebook PC, and LCD monitor applications. It is optimized for

operation between 3 to 78MHz range. In the following application schematic example, the P2781A spread percentage

selection is determined by the external LF value specified in the Loop Filter Selection Table. The

Input Frequency Selection

Table

specifies the input frequency range. The external LF allows the user to fine tune the spread percentage to optimize the

EMI reduction benefits of the spread spectrum.

+3.3V

16 MHz

XIN/CLKIN VDD

XOUT

FS1

FS0

ModOUT

2.2 K

0.1µF

Modulated 16MHz Clock

To target Chip

0 Ohm

VSS

P278xA

Note: Both logic input pins FS1 and FS0 have to be connected to either VDD or VSS. Do not leave them floating.

Rev. 2 | Page 4 of 8 | www.onsemi.com

P2781/82/84

Absolute Maximum Ratings

Symbol

, V

STG

Storage temperature

Max. Soldering Temperature (10 sec)

Junction Temperature

Static Discharge Voltage (As per JEDEC STD22- A114-B)

Parameter

Rating

-0.5 to +4.6

-65 to +125

260

150

Unit

Voltage on any pin with respect to Ground

Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect

device reliability.

Operating Conditions

Parameter

VDD

Supply Voltage

Operating Temperature (Ambient Temperature)

Load Capacitance

Input Capacitance

Description

Min

3.0

-40

Max

3.6

+85

Unit

DC Electrical Characteristics

Symbol

XOL

XOH

VDD

Input low voltage

(Test condition: All parameters are measured at room temperature (+25° unless otherwise stated.)

Parameter

Input high voltage

Input low current

(internal input pull-up resistor on FS0 and FS1)

Input high current

(internal input pull-up resistor on FS0 and FS1)

XOUT output low current

XOUT output high current

Output low voltage (VDD = 3.3V, I

= 20mA)

Output high voltage (VDD = 3.3V, I

= 20mA)

Static supply current

Typical dynamic supply current

(25pF scope probe loading)

Operating voltage

Min

VSS – 0.3

2.0

Typ

Max

0.8

VDD +0.3

Unit

µA

0.4

2.5

5.2 at 3MHz

3.0

3.3

21.2 at 82MHz

3.6

Rev. 2 | Page 5 of 8 | www.onsemi.com