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PALCE20V8-25

Flash-Erasable Reprogrammable CMOS PAL㈢ Device

厂商名称：Cypress(赛普拉斯)

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USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
PALCE20V8
Flash-Erasable Reprogrammable
CMOS PAL
®
Device
Features
• Active pull-up on data input pins
• Low power version (20V8L)
— 55 mA max. commercial (15, 25 ns)
— 65 mA max. military/industrial
(15, 25 ns)
• Standard version has low power
— 90 mA max. commercial
(15, 25 ns)
— 115 mA max. commercial (10 ns)
— 130 mA max. military/industrial (15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combina-
torial operation
• QSOP package available
— 10, 15, and 25 ns com’l version
— 15, and 25 ns military/industrial versions
• High reliability
— Proven Flash technology
— 100% programming and functional testing
Functional Description
The Cypress PALCE20V8 is a CMOS Flash Erasable
second-generation programmable array logic device. It is
implemented with the familiar sum-of-product (AND-OR) logic
structure and the programmable macrocell.
The PALCE20V8 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerdip, a 28-lead square ceramic leadless chip
carrier, a 28-lead square plastic leaded chip carrier, and a
24-lead quarter size outline. The device provides up to 20
inputs and 8 outputs. The PALCE20V8 can be electrically
erased and reprogrammed. The programmable macrocell
enables the device to function as a superset to the familiar
24-pin PLDs such as 20L8, 20R8, 20R6, 20R4.
Logic Block Diagram (PDIP/CDIP/QSOP)
GND
12
I
10
11
I
9
10
I
8
9
I
7
8
I
6
7
I
5
6
I
4
5
I
3
4
I
2
3
I
1
2
CLK/I
0
1
PROGRAMMABLE
AND ARRAY
(64 x 40)
8
8
8
8
8
8
8
8
MUX
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
MUX
13
OE/I
11
14
I
12
15
I/O
0
16
I/O
1
17
I/O
2
18
I/O
3
19
I/O
4
20
I/O
5
21
I/O
6
22
I/O
7
23
I
13
24
V
CC
Cypress Semiconductor Corporation
Document #: 38-03026 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised April 19, 2004
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Pin Configuration
DIP/QSOP
Top View
CLK/I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
10
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
I
13
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
I
12
OE/I
11
PALCE20V8
PLCC/LCC
Top View
I2
I1
CLK/I
0
NC
VCC
I13
I/O7
4 3 2 1 2827 26
I
3
I
4
I
5
NC
I
6
I
7
I
8
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O
6
I/O
5
I/O
4
NC
I/O
3
I/O
2
I/O
1
121314 1516 1718
Selection Guide
t
PD
ns
Generic Part Number
PALCE20V8−5
PALCE20V8−7
PALCE20V8−10
PALCE20V8−15
PALCE20V8−25
PALCE20V8L−15
PALCE20V8L−25
Com’l/Ind
5
7.5
10
15
25
15
25
10
15
25
15
25
Mil
3
7
10
12
15
12
15
10
12
20
12
20
t
S
ns
Com’l/Ind
Mil
4
5
7
10
12
10
12
10
12
20
12
20
t
CO
ns
Com’l/Ind
Mil
115
115
115
90
90
55
55
130
130
130
65
65
I
CC
mA
Com’l
Mil/Ind
Shaded areas contain preliminary information.
Document #: 38-03026 Rev. *B
I9
I10
GND
NC
OE/I 11
I12
I/O0
Page 2 of 14
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Functional Description
The PALCE20V8 features 8 product terms per output and 40
input terms into the AND array. The first product term in a
macrocell can be used either as an internal output enable
control or as a data product term.
There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are
selectable from either the input/output pin associated with the
macrocell, the input/output pin associated with an adjacent
pin, or from the macrocell register itself.
Power-Up Reset
All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the
associated output pin will be HIGH due to active-LOW outputs.
Electronic Signature
PALCE20V8
An electronic signature word is provided in the PALCE20V8
that consists of 64 bits of programmable memory that can
contain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the
internal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE20V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each
product term. The PTD fuses allow each product term to be
individually disabled.
Input and I/O Pin Pull-Ups
The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active HIGH
state (logical 1). All unused inputs and three-stated I/O pins
should be connected to another active input, V
CC
, or Ground
to improve noise immunity and reduce I
CC
.
Configuration Table
CG
0
0
0
1
1
1
CG
1
1
1
0
0
1
CL0
x
0
1
0
1
1
Cell Configuration
Registered Output
Combinatorial I/O
Combinatorial Output
Input
Combinatorial I/O
Devices Emulated
Registered Med PALs
Registered Med PALs
Small PALs
Small PALs
20L8 only
Macrocell
OE
V
CC
0 X
1 0
1 1
1 0
0 0
0 1
To
Adjacent
Macrocell
1 1
CG
1
CL0
x
1 1
0 X
D
Q
Q
1 0
1 1
0 X
CG
1
for pin 16 to 21 (DIP)
CG
0
for pin 15 and 22 (DIP)
CL0
x
1 0
I/O
x
V
CC
CLK
CL1
x
From
Adjacent
Pin
Document #: 38-03026 Rev. *B
Page 3 of 14
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied..................................................
−55°C
to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State
.....................................................−0.5V
to +7.0V
PALCE20V8
DC Input Voltage
................................................. −0.5V
to +7.0V
Output Current into Outputs (LOW)............................. 24 mA
DC Programming Voltage............................................. 12.5V
Latch-up Current...................................................... >200 mA
Operating Range
[1]
Range
Commercial
Industrial
Military
[2]
Ambient Temperature
0
°
C to +75
°
C
−40
°
C to +85
°
C
−55
°
C to +125
°
C
V
CC
5V
±5%
5V
±10%
5V
±10%
Electrical Characteristics
Over the Operating Range
[3]
Parameter
V
OH
V
OL
V
IH
V
IL[5]
I
IH
I
IL[6]
I
SC
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input or I/O HIGH Leakage
Current
Input or I/O LOW Leakage
Current
Operating Power Supply
Current
V
CC
= Min.,
V
IN
= V
IH
or V
IL
V
CC
= Min.,
V
IN
= V
IH
or V
IL
Test Conditions
I
OH
=
−3.2
mA
I
OH
=
−2
mA
I
OL
= 24 mA
I
OL
= 12 mA
Com’l
Mil/Ind
Com’l
Mil/Ind
2.0
−0.5
0.8
10
−100
−30
Com’l
−150
115
90
55
Mil/Ind
Mil/Ind
130
65
V
V
µA
µA
mA
mA
mA
mA
mA
mA
0.5
V
Min.
2.4
Max.
Unit
V
Guaranteed Input Logical HIGH Voltage for All Inputs
[4]
Guaranteed Input Logical LOW Voltage for All Inputs
[4]
3.5V < V
IN
< V
CC
0V < V
IN
< V
IN
(Max.)
Output Short Circuit Current V
CC
= Max., V
OUT
= 0.5V
[7,8]
V
CC
= Max.,
V
IL
= 0V, V
IH
= 3V,
Output Open,
f = 15 MHz
(counter)
5, 7, 10 ns
15, 25 ns
15L, 25L ns
10, 15, 25 ns
15L, 25L ns
Capacitance
[8]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 2.0V @ f = 1 MHz
V
OUT
= 2.0V @ f = 1 MHz
Typ.
5
5
Unit
pF
pF
Endurance Characteristics
[8]
Parameter
N
Description
Minimum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
Min.
100
Max.
Unit
Cycles
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. T
A
is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
5. V
IL
(Min.) is equal to
−
3.0V for pulse durations less than 20 ns.
6. The leakage current is due to the internal pull-up resistor on all pins.
7. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03026 Rev. *B
Page 4 of 14
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
AC Test Loads and Waveforms
ALL INPUT PULSES
3.0V
90%
GND
≤
2 ns
10%
90%
10%
≤
2 ns
PALCE20V8
5V
S1
R1
OUTPUT
R2
C
L
TEST POINT
Commercial
Specification
t
PD
, t
CO
t
PZX
, t
EA
t
PXZ
, t
ER
Closed
Z
⎜
H: Open
Z
⎜
L: Closed
H
⎜
Z: Open
L
⎜
Z: Closed
5 pF
S
1
C
L
50 pF
R
1
200Ω
R
2
390Ω
R
1
Military
R
2
750Ω
Measured Output Value
1.5V
1.5V
H
⎜
Z: V
OH
−
0.5V
L
⎜
Z: V
OL
+ 0.5V
390Ω
Commercial and Industrial Switching Characteristics
[3]
20V8−5
Parameter
t
PD
t
PZX
t
PXZ
t
EA
t
ER
t
CO
t
S
t
H
t
P
Description
Input to Output
Propagation Delay
[9]
OE to Output Enable
OE to Output Disable
Input to Output Enable
Delay
[8]
Input to Output
Disable Delay
[8,10]
Clock to Output Delay
[9]
Input or Feedback Set-up
Time
Input Hold Time
External Clock Period
(t
CO
+ t
S
)
1
3
0
7
Min.
1
Max.
5
5
5
6
6
4
1
7
0
12
20V8−7
Min.
1
Max.
7.5
6
6
9
9
5
1
10
0
17
20V8−10
Min.
1
Max.
10
10
10
10
10
7
1
12
0
22
20V8−15
Min.
1
Max.
15
15
15
15
15
10
1
15
0
27
20V8−25
Min.
1
Max.
25
20
20
25
25
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Shaded areas contain preliminary information.
Notes:
9. Min. times are tested initially and after any design or process changes that may affect these parameters.
10. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous HIGH
level has fallen to 0.5 volts below V
OH
min. or a previous LOW level has risen to 0.5 volts above V
OL
max.
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f
MAX
internal (1/f
MAX3
) as measured (see Note 7 above) minus t
S
.
Document #: 38-03026 Rev. *B
Page 5 of 14
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参数对比
与PALCE20V8-25相近的元器件有：PALCE20V8_04、PALCE20V8-10、PALCE20V8-5、PALCE20V8-7、PALCE20V8L-25、PALCE20V8L-15、PALCE20V8-15。描述及对比如下：
型号 PALCE20V8-25 PALCE20V8_04 PALCE20V8-10 PALCE20V8-5 PALCE20V8-7 PALCE20V8L-25 PALCE20V8L-15 PALCE20V8-15
描述 Flash-Erasable Reprogrammable CMOS PAL㈢ Device Flash-Erasable Reprogrammable CMOS PAL㈢ Device Flash-Erasable Reprogrammable CMOS PAL㈢ Device Flash-Erasable Reprogrammable CMOS PAL㈢ Device Flash-Erasable Reprogrammable CMOS PAL㈢ Device Flash-Erasable Reprogrammable CMOS PAL㈢ Device Flash-Erasable Reprogrammable CMOS PAL㈢ Device Flash-Erasable Reprogrammable CMOS PAL㈢ Device
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器件捷径:
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ
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