INTEGRATED CIRCUITS
PCK2014A
CK98 (100/133 MHz) spread spectrum
system clock generator
Product specification
ICL03 — PC Motherboard ICs; Logic Products Group
2001 Apr 02
Philips
Semiconductors
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014A
FEATURES
•
ESD classification testing is done to JEDEC Standard JESD22.
•
Latch-up testing is done to JEDEC Standard JESD78
•
Mixed 2.5 V and 3.3 V operation
•
Six CPU clocks at 2.5 V
•
Six PCI clocks at 3.3 V, one free-running
•
Two 3.3 V fixed clocks @ 66 MHz
•
Three 2.5 V IOAPIC clocks @ 16.67 MHz
•
One 3.3 V 48 MHz USB clock
•
Two 3.3 V reference clocks @ 14.318 MHz
•
Reference 14.31818 MHz Xtal oscillator input
•
133 MHz or 100 MHz operation
•
Power management control input pins
•
CPU clock jitter
≤
150 ps cycle-cycle
•
CPU clock skew
≤
175 ps pin-pin
•
0.0 ns – 1.5 ns CPU - 3V66 delay
•
1.5 ns – 3.5 ns 3V66 - PCI delay
•
1.5 ns – 4.0 ns CPU - IOAPIC delay
•
1.5 ns – 4.0 ns CPU - PCI delay
•
Available in 56-pin SSOP package
•
±0.6%
Center spread spectrum capability via select pins
•
–0.6% Down spread spectrum capability via select pins
DESCRIPTION
The PCK2014A is a clock generator (frequency synthesizer) chip for
a Pentium III and other similar processors.
The PCK2014A has six CPU clock outputs at 2.5 V, two 3V66 clocks
running at 66 MHz. there are six PCI clock outputs running at
33 MHz. Additionally, the part has three 2.5 V IOAPIC clock outputs
at 16.67 MHz and two 3.3 V reference clock outputs at 14.318 MHz.
All clock outputs meet Intel’s drive strength, rise/fall time, jitter,
accuracy, and skew requirements.
The part possesses dedicated power-down, CPUSTOP, and
PCISTOP input pins for power management control. These inputs
are synchronized on-chip and ensure glitch-free output transitions.
When the CPUSTOP input is asserted, the CPU clock outputs and
3V66 clock outputs are driven LOW. When the PCISTOP input is
asserted, the PCI clock outputs are driven LOW.
Finally, when the PWRDWN input pin is asserted, the internal
reference oscillator and PLLs are shut down, and all outputs are
driven LOW.
(synchronous with CPU clocks)
which exceeds 100 mA.
Protection exceeds 2000 V to HBM per method A114.
PIN CONFIGURATION
V
SS
1
REF0
REF1
V
DD
3V
XTAL_IN
XTAL_OUT
2
3
4
5
6
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
DD
25V
APIC2
APIC1
APIC0
V
SS
V
DD
25V
CPUCLK5
CPUCLK4
V
SS
V
DD
25V
CPUCLK3
CPUCLK2
V
SS
V
DD
25V
CPUCLK1
CPUCLK0
V
SS
V
DD
3V
V
SS
PCISTOP
CPUSTOP
PWRDWN
SPREAD
SEL1
SEL0
V
DD
3V
48MHz_USB
V
SS
V
SS
7
V
SS
PCI_F
8
9
V
DD
3V 10
PCI_1 11
PCI_2 12
V
SS
13
PCI_3 14
PCI_4 15
V
DD
3V 16
V
DD
3V 17
PCI_5 18
V
SS
19
V
SS
20
V
SS
21
V
DD
3V 22
V
DD
3V 23
V
SS
24
3V66_0 25
3V66_1 26
V
DD
3V 27
SEL133/100 28
SW00879
ORDERING INFORMATION
PACKAGES
56-pin plastic SSOP
TEMPERATURE RANGE
0 to +70
°C
ORDER CODE
PCK2014ADL
DRAWING NUMBER
SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
2001 Apr 02
2
853–2245 25964
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014A
PIN DESCRIPTION
PIN NUMBER
2, 3
5
6
9, 11, 12, 14, 15, 18
25, 26
28
30
32, 33
34
35
36
37
41, 42, 45, 46, 49, 50
53, 54, 55
4, 10, 16, 17,
22, 23, 27, 31, 39
1, 7, 8, 13, 19, 20, 21, 24,
29, 38, 40, 44, 48, 52
43, 47, 51, 56
SYMBOL
REF [0–1]
XTAL_IN
XTAL_OUT
PCI_[F, 1–5]
3V66 [0–1]
SEL133/100
48 MHz USB
SEL [0–1]
SPREAD
PWRDWN
CPUSTOP
PCISTOP
CPUCLK [0–5]
APIC [0–2]
V
DD3V
V
SS
V
DD25V
3.3 V 14.318 MHz clock output
14.318 MHz crystal input
14.318 MHz crystal output
3.3 V PCI clock outputs, pin 9 is a free running PCI clock
3.3 V fixed 66 MHz clock outputs
Select input pin for enabling 133 MHz or 100 MHz CPU outputs.
H = 133 MHz, L = 100 MHz
3.3 V fixed 48 MHZ clock output
Logic select pins. TTL levels.
3.3 V LVTTL input. Enables spread spectrum mode when held LOW.
3.3 V LVTTL input. Device enters powerdown mode when held LOW.
3.3 V LVTTL input. Stops all CPU clocks and 3V66 clocks when held LOW.
CPUDIV_2 output remains on all the time.
3.3 V LVTTL input. Stops all PCI clocks except PCICLK_F when held LOW.
2.5 V CPU output. 133 MHz or 100 MHz depending on state of input pin SEL133/100.
2.5 V clock outputs running divide synchronous with the CPU clock frequency.
Fixed 16.67 MHz limit.
3.3 V power supply, pins 22 and 23 are analog V
DD
.
Ground, pins 20 and 21 are analog V
SS
.
2.5 V power supply
FUNCTION
NOTE:
1. V
DD3V
, V
DD25V
and V
SS
in the above table reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on
the performance of the device. In reality, the platform will be configured with the V
DD25V
pins tied to a 2.5 V supply, all remaining V
DD
pins
tied to a common 3.3 V supply and all V
SS
pins being common.
2. Pins 20 and 21 are analog ground and should be tied to a ground plane. Pins 22 and 23 are analog V
DD
should be properly decoupled
to a 3.3 V supply. These analog power supply pins should not be tied to the PCI power and ground to avoid noise coupling into the
analog power supply pins. The PCK2014 provides separate power supplies for the internal digital circuitry (pin 39, V
CC
) and the internal
PLLs of the device (pins 22 and 23, V
CC
). The purpose of this approach is to try and isolate the high switching noise digital outputs from
relatively sensitive analog blocks. In controlled environments such as a test board this level is very well controlled. However, in a mixed
signal environment, a second level of isolation may be required.
2001 Apr 02
3
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014A
BLOCK DIAGRAM
LOGIC
PWRDWN
LOGIC
XTAL_IN X
14.318
MHZ
OSC
USBPLL
X REF [0–1](14.318 MHz)
XTAL_OUT X
PWRDWN
LOGIC
X 48 MHz USB
SPREAD X
SYSPLL
STOP
LOGIC
X CPUCLK [0–5]
SEL133/100
SEL0
SEL1
DECODE
LOGIC
STOP
LOGIC
X 3V66 [0–1] (66MHz)
STOP
LOGIC
PCISTOP X
CPUSTOP X
PWRDWN X
PWRDWN
LOGIC
X PCI_[F, 1–5] (33 MHz)
X APIC [0–2] (16.67 MHz)
SW00765
2001 Apr 02
4
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014A
FUNCTION TABLE
SEL
133/100
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
CPU
HI-Z
100 MHz
100 MHz
100 MHz
TCLK/2
133 MHz
133 MHz
133 MHz
3V66
HI-Z
66 MHz
66 MHz
66 MHz
TCLK/4
66 MHz
66 MHz
66 MHz
PCI
HI-Z
33 MHz
33 MHz
33 MHz
TCLK/8
33 MHz
33 MHz
33 MHz
48 MHz
HI-Z
48 MHz
HI-Z
48 MHz
TCLK/2
48 MHz
HI-Z
48 MHz
REF
HI-Z
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
14.318 MHz
14.318 MHz
14.318 MHz
IOAPIC
HI-Z
16.67 MHz
16.67 MHz
16.67 MHz
TCLK/16
16.67 MHz
16.67 MHz
16.67 MHz
NOTES
1
2
3
4, 7, 8
5, 6
2
3
4, 7, 8
NOTES:
1. Required for board level “bed-of-nails” testing.
2. Philips center spread mode.
3. 48 MHz PLL disabled to reduce component jitter. 48 MHz outputs to be held Hi-Z instead of driven to LOW state.
4. “Normal” mode of operation.
5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133 MHz CPU select logic.
6. Required for DC output impedance verification.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
8. Range of reference frequency allowed is MIN = 14.316 MHz, NOMINAL = 14.31818 MHz, MAX = 14.32 MHz
CLOCK OUTPUT
USBCLK
7
TARGET FREQUENCY (MHz)
48.0
ACTUAL FREQUENCY (MHz)
48.008
PPM
167
CLOCK ENABLE CONFIGURATION
CPUSTOP
X
0
0
1
1
PWRDWN
0
1
1
1
1
PCISTOP
X
0
1
0
1
CPUCLK
LOW
LOW
LOW
ON
ON
APIC
LOW
ON
ON
ON
ON
3V66
LOW
LOW
LOW
ON
ON
PCI
LOW
LOW
ON
LOW
ON
REF / 48 MHz
LOW
ON
ON
ON
ON
OSC
OFF
ON
ON
ON
ON
VCOs
OFF
ON
ON
ON
ON
NOTES:
1. LOW means outputs held static LOW as per latency requirement below
2. ON means active.
3. PWRDWN pulled LOW, impacts all outputs including REF and 48 MHz outputs.
4. All 3V66 clocks as well as CPU clocks should stop cleanly when CPUSTOP is pulled LOW.
5. CPUDIV2, IOAPIC, REF, 48 MHz signals are not controlled by the CPUSTOP functionality and are enabled all in all conditions except when
PWRDWN is LOW.
POWER MANAGEMENT REQUIREMENTS
SIGNAL
CPUSTOP
PCISTOP
PWRDWN
SIGNAL STATE
0 (DISABLED)
1 (ENABLED)
0 (DISABLED)
1 (ENABLED)
1 (NORMAL OPERATION)
0 (POWER DOWN)
LATENCY
NO. OF RISING EDGES OF FREE RUNNING PCICLK
1
1
1
1
3 ms
2 MAX
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
2001 Apr 02
5
