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PDTA114YMB
83B
PNP resistor-equipped transistor; R1 = 10 kΩ, R2 = 47 kΩ
Rev. 1 — 16 May 2012
Product data sheet
1. Product profile
1.1 General description
PNP Resistor-Equipped Transistor (RET) in a leadless ultra small DFN1006B-3
(SOT883B) Surface-Mounted Device (SMD) plastic package.
NPN complement: PDTC114YMB.
SO
T8
1.2 Features and benefits
100 mA output current capability
Reduces component count
Built-in bias resistors
Reduces pick and place costs
Simplifies circuit design
AEC-Q101 qualified
Leadless ultra small SMD plastic
package
Low package height of 0.37 mm
1.3 Applications
Low-current peripheral driver
Control of IC inputs
Replaces general-purpose transistors
in digital applications
Mobile applications
1.4 Quick reference data
Table 1.
Symbol
V
CEO
I
O
R1
R2/R1
Quick reference data
Parameter
collector-emitter
voltage
output current
bias resistor 1 (input)
bias resistor ratio
T
amb
= 25 °C
Conditions
open base
Min
-
-
7
3.7
Typ
-
-
10
4.7
Max
-50
-100
13
5.7
Unit
V
mA
kΩ
NXP Semiconductors
PDTA114YMB
PNP resistor-equipped transistor; R1 = 10 kΩ, R2 = 47 kΩ
2. Pinning information
Table 2.
Pin
1
2
3
I
G
O
Pinning information
Symbol Description
input (base)
GND (emitter)
output (collector)
1
3
2
Transparent
top view
1
R2
R1
Simplified outline
Graphic symbol
3
2
SOT883B (DFN1006B-3)
sym003
3. Ordering information
Table 3.
Ordering information
Package
Name
PDTA114YMB
DFN1006B-3
Description
Leadless ultra small plastic package; 3 solder lands;
body 1.0 x 0.6 x 0.37 mm
Version
SOT883B
Type number
4. Marking
Table 4.
Marking codes
Marking code
0001 1111
Type number
PDTA114YMB
PIN 1 INDICATION
READING DIRECTION
READING EXAMPLE:
0111
1011
MARKING CODE
(EXAMPLE)
READING DIRECTION
006aac673
Fig 1.
DFN1006B-3 (SOT883B) binary marking code description
PDTA114YMB
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 16 May 2012
2 of 11
NXP Semiconductors
PDTA114YMB
PNP resistor-equipped transistor; R1 = 10 kΩ, R2 = 47 kΩ
5. Limiting values
Table 5.
Symbol
V
CBO
V
CEO
V
EBO
V
I
I
O
I
CM
P
tot
T
j
T
amb
T
stg
[1]
Limiting values
Parameter
collector-base voltage
collector-emitter voltage
emitter-base voltage
input voltage
output current
peak collector current
total power dissipation
junction temperature
ambient temperature
storage temperature
pulsed; t
p
≤
1 ms
T
amb
≤
25 °C
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
open emitter
open base
open collector
positive
negative
Min
-
-
-
-
-
-
-
-
-
-65
-65
Max
-50
-50
-6
6
-40
-100
-100
250
150
150
150
Unit
V
V
V
V
V
mA
mA
mW
°C
°C
°C
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.
300
P
tot
(mW)
200
006aad009
100
0
-75
-25
25
75
125
175
T
amb
(°C)
FR4 PCB, standard footprint
Fig 2.
Power derating curve for DFN1006B-3 (SOT883B)
PDTA114YMB
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 16 May 2012
3 of 11
NXP Semiconductors
PDTA114YMB
PNP resistor-equipped transistor; R1 = 10 kΩ, R2 = 47 kΩ
6. Thermal characteristics
Table 6.
Symbol
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance
from junction to
ambient
Conditions
in free air
[1]
Min
-
Typ
-
Max
500
Unit
K/W
[1]
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
10
3
duty cycle =
Z
th(j-a)
(K/W)
10
2
1
0.75
0.5
0.33
0.2
0.1
0.05
0.02
10
0.01
0
006aab603
1
10
−5
10
−4
10
−3
10
−2
10
−1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, standard footprint
Fig 3.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PDTA114YMB
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 16 May 2012
4 of 11
