PRODUCT SPECIFICATION
4
PE3341
2.7 GHz Integer-N PLL
with Field-Programmable
EEPROM
Features
•
Field-programmable EEPROM
for self-starting applications
•
Standard 2.7 GHz operation,
3.0 GHz speed-grade option
•
÷10/11 dual modulus prescaler
•
Internal charge pump
•
Serial programmable
•
Low power
20mA at 3 V
•
Ultra-low phase noise
•
Available in 24-lead TSSOP or
20-lead 4x4mm MLPQ package
Product Description
Peregrine’s PE3341 is a high performance integer-N PLL
with embedded EEPROM capable of frequency synthesis
up to 2.7 GHz with a speed-grade option to 3.0 GHz. The
EEPROM allows designers to permanently store control
bits, allowing easy configuration of self-starting
synthesizers. The superior phase noise performance of
the PE3341 is ideal for applications such as sonet,
wireless base stations, fixed wireless, and RF
instrumentation systems.
The PE3341 features a ÷10/11 dual modulus prescaler,
counters, a phase comparator, and a charge pump as
shown in Figure 1. Counter values are programmable
through a three-wire serial interface.
Fabricated in Peregrine’s patented UTSi® (Ultra Thin
Silicon) CMOS technology, the PE3341 offers excellent RF
performance with the economy and integration of
conventional CMOS.
Figure 1. Block Diagram
F
in
F
in
ENH
E_WR
Data
Clock
Serial
Interface
Mux
Enhancement
Register
(8-bit)
Primary
Register
(20-bit)
EE
Register
(20-bit)
Prescaler
÷10/11
M Counter
÷2 to ÷512
13
20
Secondary
Register
(20-bit)
PD_U
Phase
Detector
Charge
Pump
PD_D
CP
20
6
20
LD
2k
6
Cext
EELoad
Transfer
Logic
V
PP
S_WR
f
r
EESel
FSel
EEPROM
R Counter
÷1 to ÷64
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Page 1 of 17
PE3341
Product Specification
Figure 2. Pin Configurations
EESel
V
DD
GND
ENH
S_WR
Data
Clock
GND
FSel
E_WR
1
2
3
4
5
6
24
23
22
21
20
19
f
r
(pin name)
NC
V
DD
GND
EESel
N/C
CP
V
DD
Dout
LD
EELoad
Cext
GND
F
in
ENH
GND
15
20
19
18
f
r
17
S_WR
Data
Clock
FSel
E_WR
16
1
2
3
4
5
CP
V
DD
Dout
LD
EELoad
24-lead TSSOP
7
8
9
18
17
16
15
14
13
20-lead
MLPQ
4x4mm
Exposed Solder Pad
(Bottom Side)
14
13
12
11
V
PP
10
V
DD
11
F
in
12
Table 1. Pin Descriptions
Pin No.
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
10
11
12
4
5
6
7
8
9
20
1
2
3
Pin No.
MLPQ
19
Pin Name
V
DD
GND
ENH
S_WR
Data
Clock
GND
FSel
E_WR
V
PP
V
DD
F
in
F
in
GND
C
EXT
EELoad
LD
Type
(Note 1)
(Note 2)
Input
Input
Input
Input
(Note 2)
Input
Input
Input
(Note 1)
Input
Input
(Note 2)
Output
Input
Output, OD
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
Ground.
Enhancement mode control line. When asserted LOW, enhancement register bits are
functional. Internal 70kΩ pull-up resistor.
Secondary Register WRITE input. Primary Register contents are copied to the
Secondary Register on S_WR rising edge. Also used to control Serial Port operation and
EEPROM programming.
Binary serial data input. Input data entered LSB (B
0
) first.
Serial clock input. Data is clocked serially into the 20-bit Primary Register, the 20-bit EE
Register, or the 8-bit Enhancement Register on the rising edge of Clock. Also used to
clock EE Register data out Dout port.
Ground.
Frequency Register selection control line. Internal 70kΩ pull-down resistor.
Enhancement Register write enable. Also functions as a Serial Port control line. Internal
70kΩ pull-down resistor.
EEPROM erase/write programming voltage supply pin. Requires a 100pF bypass
capacitor connected to GND.
Same as pin 1.
Prescaler input from the VCO.
Prescaler complementary input. A series 50
Ω
resistor and DC blocking capacitor should
be placed as close as possible to this pin and connected to the ground plane.
Ground.
Logical “NAND” of PD_U and PD_D terminated through an on-chip, 2kΩ series resistor.
Connecting C
EXT
to an external capacitor will low pass filter the input to the inverting
amplifier used for driving LD.
Control line for Serial Data Port, Frequency Register selection, EE Register parallel
loading, and EEPROM programming. Internal 70kΩ pull-down resistor.
Lock detect output, an open-drain logical inversion of C
EXT
. When the loop is in lock, LD
is high impedance; otherwise, LD is a logic LOW.
File No. 70/0053~03D
C
EXT
F
IN
V
DD
V
PP
F
IN
10
6
7
8
9
Copyright
Peregrine Semiconductor Corp. 2003
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CMOS RFIC SOLUTIONS
Page 2 of 17
PE3341
Product Specification
Pin No.
TSSOP
18
19
20
21
22
23
24
Pin No.
MLPQ
13
14
15
16
17
Pin Name
Dout
V
DD
CP
N/C
EESel
GND
Type
Output
(Note 1)
Output
Description
Data out function. Dout is defined with the Enhancement Register and enabled with ENH.
Same as pin 1.
Charge pump output. Sources current is when f
c
leads f
p
and sinks current when f
c
lags
f
p
.
No connection.
Control line for Frequency Register selection, EE Register parallel loading, and EEPROM
programming. Internal 70kΩ pull-up resistor.
Ground.
Reference frequency input.
Input
(Note 2)
Input
18
f
r
Notes 1:
V
DD
pins 1, 11, and 19 (TSSOP) or pins 6, 14 and 19 (MLPQ), are connected by diodes and must be supplied with the same positive voltage
level.
2:
Ground connections are made through the exposed solder pad. The solder pad must be soldered to the ground plane for proper operation.
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
Stg
Electrostatic Discharge (ESD) Precautions
Max
+4.0
V
DD
+0.3
+85
Parameter/Conditions
Supply voltage
Voltage on any digital input
Storage temperature range
Min
–0.3
–0.3
–65
Units
V
V
°C
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient
temperature range
Min
2.85
-40
Max
3.15
85
Units
V
°C
Table 4. ESD Ratings
Symbol
V
ESD
V
ESD
(V
PP
)
Note 1:
Parameter/Conditions
ESD voltage human body
model (Note 1)
ESD voltage human body
model (Note 1)
Min
Max
1000
200
Units
V
V
Periodically sampled, not 100% tested. Tested per MIL-STD-883,
M3015 C2
Table 5. DC Characteristics
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Page 3 of 17
PE3341
Product Specification
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
I
DD
Parameter
Operational supply current;
Prescaler enabled
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
EEPROM write voltage
EEPROM erase voltage
EEPROM write cycle current
EEPROM erase cycle current
High-level input current
Low-level input current
Output voltage LOW
Output voltage HIGH
Output voltage LOW, C
EXT
Output voltage HIGH, C
EXT
Output voltage LOW, LD
Drive current
Drive current
Leakage current
Sink vs. source mismatch
Output current magnitude variation vs. voltage
Conditions
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
Min
Typ
20
Max
30
Units
mA
V
Digital Inputs: S_WR, Data, Clock
V
IH
V
IL
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
V
PP
_WRITE
V
PP
_ERASE
I
PP
_WRITE
I
PP
_ERASE
I
IHR
I
ILR
V
OLD
V
OHD
V
OLC
V
OHC
V
OLLD
I
CP
– Source
I
CP
– Sink
I
CPL
VS.
0.7 x V
DD
0.3 x V
DD
+1
-1
0.7 x V
DD
0.3 x V
DD
+1
-100
0.7 x V
DD
0.3 x V
DD
+100
-1
12.5
-8.5
30
-10
V
µA
µA
V
V
µA
µA
V
V
µA
µA
V
V
mA
mA
Digital inputs: ENH, EESel (contains a 70 kΩ pull-up resistor)
Digital inputs: FSel, EELoad, E_WR (contains a 70 kΩ pull-down resistor)
EE Memory Programming Voltage and Current: V
PP
, I
PP
Reference Divider input: f
r
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
I
out
= 6 mA
I
out
= -3 mA
I
out
= 0.1 mA
I
out
= -0.1 mA
I
out
= 1 mA
V
CP
= V
DD
/ 2
V
CP
= V
DD
/ 2
1.0 V < V
CP
< V
DD
– 1.0 V
V
CP
= V
DD
/ 2, T
A
= 25° C
1.0 V < V
CP
< V
DD
– 1.0 V
T
A
= 25° C
-2.6
1.4
-1
-2
2
V
DD
- 0.4
0.4
-1.4
2.6
1
15
15
V
DD
- 0.4
0.4
-100
0.4
+100
µA
µA
V
V
V
V
V
mA
mA
µA
%
%
Counter output: Dout
Lock detect outputs: (C
EXT
, LD)
Charge Pump output: CP
I
CP
- Source
I
CP
– Sink
I
CP VS.
V
CP
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0053~03D
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UTSi
CMOS RFIC SOLUTIONS
Page 4 of 17
PE3341
Product Specification
Table 6. AC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
f
Clk
t
ClkH
t
ClkL
t
DSU
t
DHLD
t
PW
t
CWR
t
CE
t
WRC
t
EC
Parameter
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Data set-up time to Clock rising edge
Data hold time after Clock rising edge
S_WR pulse width
Clock rising edge to S_WR rising edge
Clock falling edge to E_WR transition
S_WR falling edge to Clock rising edge
E_WR transition to Clock rising edge
(Note 1)
Conditions
Min
Max
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface and Registers (see Figure 3)
30
30
10
10
30
30
30
30
30
500
25
(Note 2)
1
300
Speed-grade option (Note 3)
External AC coupling
(Note 4)
External AC coupling (Note 4)
(Note 5)
Single ended input
(Note 6)
-2
20
-75
-85
300
-5
50
-5
2700
3000
5
270
5
100
30
EEPROM Erase/Write Programming (see Figures 4 & 5)
t
EESU
EELoad rising edge to V
PP
rising edge
t
EEPW
t
VPP
F
In
F
In
P
FIn
F
In
P
FIn
Reference Divider
f
r
P
fr
Phase Detector
f
c
Comparison frequency
100 Hz Offset
1 kHz Offset
Note 1:
Operating frequency
Reference input power (Note 4)
V
PP
pulse width
V
PP
pulse rise and fall times
Operating frequency
Operating frequency
Input level range
Operating frequency
Input level range
ms
µs
MHz
MHz
dBm
MHz
dBm
MHz
dBm
MHz
dBc/Hz
dBc/Hz
Main Divider (Including Prescaler)
Main Divider (Prescaler Bypassed)
SSB Phase Noise (F
in
= 1.3 GHz, f
r
= 10 MHz, f
c
= 1.25 MHz, LBW = 70 kHz, V
DD
= 3.0 V, Temp = -40° C
)
f
Clk
is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify f
Clk
specification.
Rise and fall times of the V
PP
programming voltage pulse must be greater than 1
µs.
The maximum frequency of operation can be extended to 3.0 GHz by ordering a special speed-grade option. Please refer to Table 14, Ordering
Information, for ordering details.
Note 2:
Note 3:
Note 4:
CMOS logic levels can be used to drive F
In
input if DC coupled and used in Prescaler Bypass mode. Voltage input needs to be a minimum of
0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. No minimum frequency
limit exists when operated in this mode.
Note 5:
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase
noise performance, the reference input falling edge rate should be faster than 80 mV/ns.
Note 6:
Parameter is guaranteed through characterization only and is not tested.
Functional Description
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Page 5 of 17
