Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
FEATURES
•
’Trench’
technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
PHP24N03LT, PHB24N03LT
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 30 V
I
D
= 24 A
g
s
R
DS(ON)
≤
56 mΩ (V
GS
= 5 V)
R
DS(ON)
≤
50 mΩ (V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP24N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB24N03LT is supplied in the SOT404 surface mounting package.
PINNING
PIN
1
2
3
tab
gate
drain
1
source
drain
DESCRIPTION
SOT78 (TO220AB)
tab
SOT404
tab
2
1 23
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 175˚C
T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ
T
mb
= 25 ˚C; V
GS
= 5 V
T
mb
= 100 ˚C; V
GS
= 5 V
T
mb
= 25 ˚C
T
mb
= 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
±
13
24
20
96
60
175
UNIT
V
V
V
A
A
A
W
˚C
1
It is not possible to make connection to pin 2 of the SOT404 package.
January 1998
1
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
ESD LIMITING VALUE
SYMBOL PARAMETER
V
C
Electrostatic discharge
capacitor voltage, all pins
CONDITIONS
PHP24N03LT, PHB24N03LT
MIN.
-
MAX.
2
UNIT
kV
Human body model (100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
R
th j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
MIN.
-
SOT78 package, in free air
SOT404 package, pcb mounted, minimum
footprint
-
-
TYP. MAX. UNIT
-
60
50
2.5
-
-
K/W
K/W
K/W
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
(BR)GSS
V
GS(TO)
R
DS(ON)
g
fs
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
C
iss
C
oss
C
rss
Drain-source breakdown
voltage
Gate-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
I
G
= 1 mA
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
GS
= 5 V; I
D
= 25 A
V
GS
= 10 V; I
D
= 25 A
V
GS
= 5 V; I
D
= 12 A; T
j
= 175˚C
Forward transconductance
V
DS
= 25 V; I
D
= 12 A
Gate-source leakage current V
GS
=
±5
V; V
DS
= 0 V;
T
j
= 175˚C
Zero gate voltage drain
V
DS
= 30 V; V
GS
= 0 V;
current
T
j
= 175˚C
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
I
D
= 10 A; V
DD
= 30 V; V
GS
= 5 V
MIN.
30
27
10
1
0.5
-
-
-
-
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
-
1.5
-
-
50
45
-
5
0.02
-
0.05
-
9
2.3
5.4
12
50
30
36
3.5
4.5
7.5
460
144
78
-
-
-
2
-
2.3
56
50
104
-
1
10
10
500
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
mΩ
mΩ
mΩ
S
µA
µA
µA
µA
nC
nC
nC
ns
ns
ns
ns
nH
nH
nH
pF
pF
pF
V
DD
= 30 V; I
D
= 25 A;
V
GS
= 5 V; R
G
= 10
Ω
Resistive load
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
January 1998
2
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
PHP24N03LT, PHB24N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 12 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 25 V
-
-
-
TYP. MAX. UNIT
-
-
1.05
50
0.1
24
96
1.5
-
-
A
A
V
ns
µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W
DSS
CONDITIONS
MIN.
-
MAX.
15
UNIT
mJ
Drain-source non-repetitive I
D
= 12 A; V
DD
≤
15 V;
unclamped inductive turn-off V
GS
= 5 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
energy
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
0
20
40
60
80 100
Tmb / C
120
140
160
180
0
20
40
60
80 100
Tmb / C
120
140
160
180
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
January 1998
3
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
PHP24N03LT, PHB24N03LT
100
ID, Drain current (Amps)
D
=V
ID
S/
PHP24N03T
0.12
0.1
0.08
RDS(on), Drain-Source on resistance (Ohms)
PHP24N03LT
3V
VGS = 2.5 V
RD
S(
)
ON
10 us
100 us
10
DC
1 ms
10 ms
Tmb = 25 C
1
0
0.06
0.04
0.02
Tj = 25 C
3.5 V
5V
15 V
1
10
VDS, Drain-source voltage (Volts)
100
0
5
10
15
ID, Drain current (Amps)
20
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Transient thermal impedance, Zth j-mb (K/W) PHP24N03T
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
10
20
Drain current, ID (A)
VDS = 25 V
PHP24N03LT
D=
1
0.5
0.2
0.1
0.05
0.1
0.02
P
D
t
p
D=
t
p
T
t
15
10
0
T
5
175 C
Tj = 25 C
0.01
1us
10us 100us 1ms 10ms
pulse width, tp (s)
0.1s
1s
10s
0
0
1
2
3
Gate-source voltage, VGS (V)
4
5
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
ID, Drain current (Amps)
5V
15 V
PHP24N03LT
3.5 V
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
); parameter T
j
PHP24N03LT
20
15
Transconductance, gfs (S)
VDS = 25 V
Tj = 25 C
15
10
10
3V
175 C
5
5
VGS = 2.5 V
Tj = 25 C
0
0
5
10
15
20
25
VDS, Drain-Source voltage (Volts)
30
0
0
5
10
Drain current, ID (A)
15
20
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
)
January 1998
4
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
PHP24N03LT, PHB24N03LT
a
2
30V TrenchMOS
1000
Capacitances Ciss, Coss, Crss (pF)
Ciss
PHP24N03LT
1.5
1
100
Coss
Crss
0.5
Tj = 25 C
0
-100
-50
0
50
Tj / C
100
150
200
10
1
10
100
Drain-source voltage, VDS (V)
1000
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 12 A; V
GS
= 5 V
VGS(TO) / V
max.
2
typ.
1.5
min.
1
BUK959-60
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
VGS, Gate-Source voltage (Volts)
VDD = 30 V
ID = 10 A
Tj = 25 C
10
2.5
15
PHP24N03LT
5
0.5
0
0
-100
-50
0
50
Tj / C
100
150
200
0
5
10
15
Qg, Gate charge (nC)
20
25
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Sub-Threshold Conduction
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
PHP24N03LT
1E-01
20
Source-Drain diode current, IF(A)
VGS = 0 V
1E-02
2%
typ
98%
15
1E-03
10
1E-04
5
175 C
Tj = 25 C
1E-05
0
0
0.2
0.4
0.6
0.8
1
Source-Drain voltage, VSDS (V)
1.2
1.4
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); parameter T
j
January 1998
5
Rev 1.300
DSP 与 ARM 处理器
