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PU7457

Silicon N-Channel Power F-MOS FET (with built-in zener diode)

器件类别:分立半导体    晶体管   

厂商名称:Panasonic(松下)

厂商官网:http://www.panasonic.co.jp/semicon/e-index.html

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器件参数
参数名称
属性值
包装说明
IN-LINE, R-PSIP-T10
针数
10
Reach Compliance Code
unknow
ECCN代码
EAR99
雪崩能效等级(Eas)
22.5 mJ
配置
2 BANKS, COMMON SOURCE, 2 ELEMENTS WITH BUILT-IN DIODE AND RESISTOR
最小漏源击穿电压
85 V
最大漏极电流 (Abs) (ID)
3 A
最大漏极电流 (ID)
3 A
最大漏源导通电阻
0.6 Ω
FET 技术
METAL-OXIDE SEMICONDUCTOR
JESD-30 代码
R-PSIP-T10
元件数量
4
端子数量
10
工作模式
ENHANCEMENT MODE
最高工作温度
150 °C
封装主体材料
PLASTIC/EPOXY
封装形状
RECTANGULAR
封装形式
IN-LINE
极性/信道类型
N-CHANNEL
最大功率耗散 (Abs)
15 W
最大脉冲漏极电流 (IDM)
9 A
认证状态
Not Qualified
表面贴装
NO
端子形式
THROUGH-HOLE
端子位置
SINGLE
晶体管应用
SWITCHING
晶体管元件材料
SILICON
Base Number Matches
1
文档预览
Power Transistor Arrays (F-MOS FETs)
PU7457
Silicon N-Channel Power F-MOS FET (with built-in zener diode)
s
Features
q
High avalanche energy capacity
q
High electrostatic breakdown voltage
q
No secondary breakdown
q
High breakdown voltage, large allowable power dissipation
q
Allowing Low-voltage drive
25.3±0.2
1.65±0.2
9.5±0.2
8.0
unit: mm
4.0±0.2
s
Applications
q
Contactless relay
q
Diving circuit for a solenoid
q
Driving circuit for a motor
q
Control equipment
q
Switching power supply
4.4±0.5
0.5±0.15
1.0±0.25
2.54±0.2
9!2.54=22.86±0.25
0.8±0.25
0.5±0.15
C1.5±0.5
s
Absolute Maximum Ratings
(T
C
= 25°C)
Parameter
Drain to Source breakdown voltage
Gate to Source voltage
Drain current
Avalanche energy capacity
Allowable power
dissipation
Channel temperature
Storage temperature
*
1
2
3
4
5
6
7
8
9 10
Symbol
V
DSS
V
GSS
I
D
I
DP
EAS
*
P
D
T
ch
T
stg
Ratings
100 ± 15
±20
±3
±9
22.5
15
3.5
150
−55
to +150
Unit
V
V
A
A
mJ
W
°C
°C
1
10
2
3
5
7
9
DC
Pulse
Non repetition
T
C
= 25°C
Ta = 25°C
G: Gate
D: Drain
S: Source
10-Lead Plastic SIL Package
Internal Connection
4
6
8
L = 5mH, I
L
= 3A, 1 pulse
s
Electrical Characteristics
(T
C
= 25°C)
Parameter
Drain to Source cut-off current
Gate to Source leakage current
Drain to Source breakdown voltage
Gate threshold voltage
Drain to Source ON-resistance
Forward transfer admittance
Diode forward voltage
Symbol
I
DSS
I
GSS
V
DSS
V
th
R
DS(on)1
R
DS(on)2
| Y
fs
|
V
DSF
C
oss
t
on
t
f
t
d(off)
Conditions
V
DS
= 80V, V
GS
= 0
V
GS
= ±20V, V
DS
= 0
I
D
= 1mA, V
GS
= 0
V
DS
= 10V, I
D
= 1mA
V
GS
= 10V, I
D
= 2A
V
GS
= 4V, I
D
= 2A
V
DS
= 10V, I
D
= 2A
I
DR
= 3A, V
GS
= 0
130
V
DS
= 10V, V
GS
= 0, f = 1MHz
160
25
V
GS
= 10V, I
D
= 2A
V
DD
= 50V, R
L
= 25Ω
0.2
0.3
1.5
2.5
85
1
300
400
4
−1.6
min
typ
max
10
±10
115
2.5
450
600
Unit
µA
µA
V
V
mΩ
mΩ
S
V
pF
pF
pF
µs
µs
µs
Input capacitance (Common Source) C
iss
Output capacitance (Common Source)
Reverse transfer capacitance (Common Source) C
rss
Turn-on time
Fall time
Turn-off time (delay time)
1
Power Transistor Arrays (F-MOS FETs)
Area of safe operation (ASO)
100
30
10
3
1
0.3
0.1
0.03
0.01
1
3
10
30
100
300
1000
I
DP
t=100µs
I
D
1ms
10ms
100ms
DC
24
PU7457
EAS
T
j
25
P
D
Ta
Avalanche energy capacity EAS (mJ)
Allowable power dissipation P
D
(W)
(1) T
C
=Ta
(2) With a 50
×
50
×
2mm
Al heat sink
(3) Without heat sink
Non repetitive pulse
T
C
=25˚C
I
D
=3A
20
20
Drain current I
D
(A)
16
(1)
12
15
10
8
(2)
4
5
(3)
0
0
20
40
60
80 100 120 140 160
0
25
50
75
100
125
150
Drain to source voltage V
DS
(V)
Ambient temperature Ta (˚C)
Junction temperature T
j
(˚C)
IAS
L-load
10
T
C
=25˚C
8
7
I
D
V
GS
6
V
DS
=10V
T
C
=25˚C
V
th
T
C
V
DS
=10V
I
D
=1mA
5
Avalanche current IAS (A)
3
I
D
Drain current I
D
(A)
22.5mJ
1
6
5
4
3
2
1
0
Gate threshold voltage V
th
(V)
0
1
2
3
4
5
6
4
0.3
3
0.1
2
0.03
1
0.01
1
3
10
30
100
0
0
25
50
75
100
125
150
L-load (mH)
Gate to source voltage V
GS
(V)
Case temperature T
C
(˚C)
I
D
V
DS
Drain to source ON-resistance R
DS(on)
(
)
8
7
V
GS
=10V
6
5
4
3
3V
2
1
0
0
10
20
30
40
600
R
DS(on)
I
D
5
| Y
fs
|
I
D
Forward transfer admittance |Y
fs
| (S)
T
C
=25˚C
V
DS
=10V
T
C
=25˚C
4
500
V
GS
=4V
Drain current I
D
(A)
4V
3.5V
400
3
300
10V
200
2
100
1
2.5V
15W
50
60
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Drain to source voltage V
DS
(V)
Drain current I
D
(A)
Drain current I
D
(A)
2
Power Transistor Arrays (F-MOS FETs)
C
iss
, C
oss
, C
rss
V
DS
Input capacitance (Common source), Output capacitance (Common source),
Reverse transfer capacitance (Common source) C
iss
,C
oss
,C
rss
(pF)
10
4
f=1MHz
T
C
=25˚C
80
PU7457
t
on
, t
f
, t
d(off)
I
D
16
I
D
=3A
T
C
=25˚C
14
12
10
V
DS
=25V
8
50V
6
4
2
V
DS
0
12
4.0
3.5
V
DD
=50V
V
GS
=10V
T
C
=25˚C
V
DS
, V
GS
Q
g
Drain to source voltage V
DS
(V)
Gate to source voltage V
GS
(V)
70
60
50
40
30
20
10
0
10
3
Switching time t
on
,t
f
,t
d(off)
(
µs
)
3.0
2.5
2.0
1.5
1.0
0.5
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
t
d(off)
C
oss
10
2
C
iss
C
rss
10
V
GS
t
f
t
on
1
0
20
40
60
80
100
0
2
4
6
8
10
Drain to source voltage V
DS
(V)
Gate charge amount Q
g
(nC)
Drain current I
D
(A)
P
ZSM
t
p
10000
3000
t
p
1000
300
100
30
10
3
1
0.1
Zener diode power P
ZSM
(W)
0.3
1
3
10
30
100
Pulse width t
p
(ms)
3
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