PYA28C256
32K x 8 EEPROM
FEATURES
Access Times of 150, 200, 250 and 350ns
Single 5V±10% Power Supply
Simple Byte and Page Write
Low Power CMOS:
- 60 mA Active Current
- 300 µA Standby Current
Fast Write Cycle Times
Software Data Protection
CMOS & TTL Compatible Inputs and Outputs
Endurance:
- 10,000 Write Cycles
- 100,000 Write Cycles (optional)
Data Retention: 10 Years
Available in the following package:
– 28-Pin 600 mil Ceramic DIP
– 32-Pin Ceramic LCC (450x550 mils)
DESCRIPTIOn
The PYA28C256 is a 5 Volt 32Kx8 EEPROM. The device
supports 64-byte page write operation. The PYA28C256
features
DATA
and Toggle Bit Polling as well as a system
software scheme used to indicate early completion of a
Write Cycle. The device also includes user-optional soft-
ware data protection. Data Retention is 10 Years. The
device is available in a 28-Pin 600 mil wide Ceramic DIP
and 32-Pin LCC.
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOn
DIP (C5-1)
LCC (L6)
Document #
EEPROM104
REV 02
Revised March 2014
PYA28C256 - 32K x 8 EEPROM
OPERATIOn
READ
Read operations are initiated by both
OE
and
CE
LOW.
The read operation is terminated by either
CE
or
OE
re-
turning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either
OE
or
CE
is HIGH.
BYTE WRITE
Write operations are initiated when both
CE
and
WE
are
LOW and
OE
is HIGH. The PYA28C256 supports both a
CE
and
WE
controlled write cycle. That is, the address is
latched by the falling edge of either
CE
or
WE,
whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either
CE
or
WE,
whichever occurs first. A
byte write operation, once initiated, will automatically con-
tinue to completion.
PAgE WRITE
The page write feature of the PYA28C256 allows 1 to
64 bytes of data to be consecutively written to the PY-
A28C256 during a single internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the source
address), but the page address (A
6
through A
14
) for each
subsequent valid write cycle to the part during this opera-
tion must be the same as the initial page address. The
bytes within the page to be written are specified with the
A
0
through A
5
inputs.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional 1 to 63 bytes in the same man-
ner as the first byte was written. Each successive byte
load cycle, started by the
WE
HIGH to LOW transition,
must begin within 150µs of the falling edge of the pre-
ceding
WE.
If a subsequent
WE
HIGH to LOW transition
is not detected within 150µs, the internal automatic pro-
gramming cycle will commence. There is no page write
window limitation. Effectively, the page write window is
infinitely wide, so long as the host continues to access the
device within the byte load cycle time of 150µs.
WRITE STATUS BITS
The PYA28C256 provides the user two write operation
status bits. These can be used to optimize a system write
cycle time. The status bits are mapped onto the I/O bus
as shown below.
DATA POLLIng
The PYA28C256 features
DATA
Polling as a method to in-
dicate to the host system that the byte write or page write
cycle has completed.
DATA
Polling allows a simple bit
test operation to determine the status of the PYA28C256,
eliminating additional interrupts or external hardware. Dur-
ing the internal programming cycle, any attempt to read
the last byte written will produce the complement of that
data on I/O
7
(i.e., write data=0xxx xxxx, read data=1xxx
xxxx). Once the programming cycle is complete, I/O
7
will
reflect true data. Note: If the PYA28C256 is in the pro-
tected state and an illegal write operation is attempted,
DATA
Polling will not operate.
TOggLE BIT
The PYA28C256 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle, I/O
6
will toggle from HIGH
to LOW and LOW to HIGH on subsequent attempts to
read the device. When the internal cycle is complete the
toggling will cease and the device will be accessible for
addtional read or write operations.
Document #
EEPROM104
REV 02
Page 2
PYA28C256 - 32K x 8 EEPROM
MAxIMUM RATIngS
(1)
Sym
V
CC
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
6.25V)
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.3 to +6.25
-0.5 to +6.25
-55 to +125
-55 to +125
-65 to +150
1.0
50
Unit
V
V
°C
°C
°C
W
mA
RECOMMEnDED OPERATIng COnDITIOnS
grade
(2)
Military
Ambient Temp
-55°C to +125°C
gnD
0V
V
CC
5.0V ± 10%
CAPACITAnCES
(4)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
10
10
Unit
pF
pF
Input Capacitance
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
IH
V
IL
V
HC
V
LC
V
OL
V
OH
I
LI
I
LO
I
SB
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Output Low Voltage (TTL Load)
Output High Voltage (TTL Load)
Input Leakage Current
Output Leakage Current
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
PYA28C010
Min
2.0
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
I
OL
= +2.1 mA, V
CC
= Min
I
OH
= -0.4 mA, V
CC
= Min
V
CC
= Max
V
IN
= GND to V
CC
V
CC
= Max,
CE
= V
IH
,
V
OUT
= GND to V
CC
CE
≥ V
IH
,
OE
= V
IL
,
Standby Power Supply Current (TTL Input Levels)
V
CC
= Max,
f = Max, Outputs Open
CE
≥ V
HC
,
I
SB1
Standby Power Supply Current (CMOS Input Levels)
V
CC
= Max,
f = 0, Outputs Open,
V
IN
≤ V
LC
or V
IN
≥ V
HC
CE
=
OE
= V
IL
,
I
CC
Supply Current
WE
= V
IH
,
All I/O's = Open,
Inputs = V
CC
= 5.5V
notes:
1. Stresses greater than those listed under
MAxIMuM RAtINGs
may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAxIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than -3.0V and -100mA,
respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
—
—
—
Max
V
CC
+ 0.3
0.8
V
CC
+ 0.5
0.2
0.4
Unit
V
V
V
V
V
V
2.4
-10
-10
+10
+10
µA
µA
3
mA
300
µA
60
mA
Document #
EEPROM104
REV 02
Page 3
PYA28C256 - 32K x 8 EEPROM
POWER-UP TIMIng
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read operation
Power-up to Write operation
Max
100
5
Unit
µs
ms
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
AVAV
t
AVQV
t
ELQV
t
OLQV
t
ELQx
t
EHQZ
t
OLQx
t
OHQZ
t
AVQx
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Chip Disable to to Output in High Z
Output Enable to Output in Low Z
Output Disable to Output in High Z
Output Hold from Address Change
0
0
50
0
0
50
0
55
0
-150
Min
120
120
120
70
0
55
0
60
0
Max
Min
150
150
150
80
0
60
0
70
-200
Max
Min
200
200
200
100
0
70
-250
Max
Min
350
350
350
100
-350
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMIng WAVEFORM OF READ CYCLE
Document #
EEPROM104
REV 02
Page 4
PYA28C256 - 32K x 8 EEPROM
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Symbol
t
WHWL1
t
EHEL1
t
AVEL
t
AVWL
t
ELAx
t
WLAx
t
WLEL
t
ELWL
t
WHEH
t
OHEL
t
OHWL
t
WHOL
t
ELEH
t
WLWH
t
DVEH
t
DVWH
t
EHDx
t
WHDx
t
EHEL2
t
WHWL2
t
ELWL
t
OVHWL
t
EHWH
t
WHOH
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
OE
Setup Time
OE
Hold Time
WE
Pulse Width
Data Setup Time
Data Hold Time
Byte Load Cycle Time
CE
Setup Time
Output Setup Time
CE
Hold Time
OE
Hold Time
0
50
0
0
10
10
100
50
0
0.2
1
1
1
1
150
150 / 200 / 250 / 350
Min
Max
10
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
Document #
EEPROM104
REV 02
Page 5
