Intel® 80332 I/O Processor
Datasheet
Product Features
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Integrated Intel XScale
®
core
— 500, 667 and 800 MHz
— ARM* V5TE Compliant
— 32 KByte, 32-way Set Associative
Instruction Cache with cache locking
— 32 KByte, 32-way Set Associative Data
Cache with cache locking. Supports
write through or write back
— 2 KByte, 2-way Set Associative
Mini-Data Cache
— 128-Entry Branch Target Buffer
— 8-Entry Write Buffer
— 4-Entry Fill and Pend Buffer
— Performance Monitor Unit
— Internal Bus 266 MHz/64-bit
PCI Express-to-PCI Bridges
— x8 PCI Express Upstream Link
— PCI Express Specification 1.0a
compliant
— PCI-X Bus A (IOP bus - ATU interface)
—PCI-X Bus B (Slot Expansion bus)
supports standard PCI Hot-Plug Controller
— Four output clocks per PCI-X bus
Address Translation Unit
— 2 KB or 4 KB Outbound Read Queue
— 4 KB Outbound Write Queue
— 4 KB Inbound Read and Write Queue
— Connects Internal Bus to PCI/X Bus A
— Messaging Unit and Expansion ROM
Two Programmable 32-bit Timers and
Watchdog Timer
Eight General Purpose I/O Pins
Two I
2
C Bus Interface Units
Warning:
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Memory Controller
— PC2700 Double Data Rate (DDR333)
SDRAM
— DDRII 400 SDRAM
— Up to 2 GB of 64-bit DDR333
— Up to 1 GB of 64-bit DDRII400
— Optional Single-bit Error Correction,
Multi-bit Detection Support (ECC)
— Supports Unbuffered or Registered
DIMMs and Discrete SDRAM
— 32-bit memory support
DMA Controller
— Two Independent Channels Connected
to Internal Bus
— Two 1KB Queues in Ch0 and Ch1
— CRC-32C Calculation
Application Accelerator Unit
— Performs optional XOR on Read Data
— Compute Parity Across Local Memory
Blocks
— 1 KB/512-byte Store Queue
Two UART (16550) Units
— 64-byte Receive and Transmit FIFOs
— 4-pin, Master/Slave Capable
Peripheral Bus Interface
— 8-/16-bit Data Bus with Two Chip Selects
Interrupt Controller Unit
— Four Priority Levels
— Vector Generation
— Sixteen External Interrupt Pins with
High Priority Interrupt (HPI#)
829-Ball, Flip Chip Ball Grid Array (FCBGA)
— 37.5 mm
2
and 1.27 mm ball pitch
Intel Corporation products are not intended for use in life support appliances,
devices or systems. Use of a Intel products in such applications without written
consent is prohibited.
Document Number: 274066-004US
August 2005
Intel® 80332 I/O Processor Datasheet
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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August 2005
Document Number: 274066-004US
Intel® 80332 I/O Processor Datasheet
Contents
1.0
Introduction......................................................................................................................... 7
1.1
About This Document............................................................................................ 7
1.1.1 Terminology.............................................................................................. 7
1.1.2 Other Relevant Documents ...................................................................... 8
About the Intel
®
80332 I/O Processor ................................................................... 9
Intel XScale
®
Core ..............................................................................................11
PCI Express-to-PCI Bridge Units ........................................................................11
Address Translation Unit .....................................................................................12
Memory Controller...............................................................................................12
Application Accelerator Unit ................................................................................12
Peripheral Bus Interface......................................................................................12
DMA Controller....................................................................................................12
I
2
C Bus Interface Unit..........................................................................................13
Messaging Unit....................................................................................................13
Internal Bus .........................................................................................................13
UART Units .........................................................................................................13
Interrupt Controller Unit .......................................................................................13
GPIO ...................................................................................................................14
SMBus Unit .........................................................................................................14
Functional Signal Descriptions ............................................................................15
Package Thermal Specifications .........................................................................56
Absolute Maximum Ratings.................................................................................57
V
CCPLL
Pin Requirements ...................................................................................57
Targeted DC Specifications.................................................................................58
Targeted AC Specifications.................................................................................60
4.4.1 Clock Signal Timings..............................................................................60
4.4.2 DDR/DDR-II SDRAM Interface Signal Timings ......................................62
4.4.3 Peripheral Bus Interface Signal Timings ................................................64
4.4.4 I
2
C/SMBus Interface Signal Timings ......................................................66
4.4.5 UART Interface Signal Timings ..............................................................66
4.4.6 PCI Express Differential Transmitter (Tx) Output Specifications............67
4.4.7 PCI Express Differential Receiver (Rx) Input Specifications ..................68
4.4.8 Boundary Scan Test Signal Timings ......................................................69
AC Timing Waveforms ........................................................................................70
AC Test Conditions .............................................................................................74
1.2
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.0
3.1
3.2
4.0
4.1
4.2
4.3
4.4
Features ...........................................................................................................................11
Package Information ........................................................................................................15
Electrical Specifications....................................................................................................57
4.5
4.6
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Intel® 80332 I/O Processor Datasheet
Figures
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Intel
®
80332 I/O Processor Functional Block Diagram ....................................... 10
829-Ball FCBGA Package Diagram .................................................................... 36
Intel
®
80332 I/O Processor Signal Group Locations (Bottom View) ................... 37
Intel
®
80332 I/O Processor Ballout - Left Side (Bottom View) ............................ 38
Intel
®
80332 I/O Processor Ballout - Right Side (Bottom View) .......................... 39
Clock Timing Measurement Waveforms ............................................................. 70
Output Timing Measurement Waveforms ........................................................... 70
Input Timing Measurement Waveforms .............................................................. 71
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C/SMBus Interface Signal Timings ................................................................... 71
UART Transmitter Receiver Timing .................................................................... 71
DDR SDRAM Write Timings ............................................................................... 72
DDR SDRAM Read Timings ............................................................................... 72
Write PreAmble/PostAmble Durations ................................................................ 73
AC Test Load for All Signals Except PCI and DDR SDRAM .............................. 74
AC Test Load for DDR SDRAM Signals ............................................................. 74
PCI/PCI-X TOV(max) Rising Edge AC Test Load............................................... 74
PCI/PCI-X TOV(max) Falling Edge AC Test Load .............................................. 75
PCI/PCI-X TOV(min) AC Test Load .................................................................... 75
Transmitter Test Load (100 ohm differential load) .............................................. 75
Transmitter Eye Diagram .................................................................................... 76
Receiver Eye Opening (Differential).................................................................... 76
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Document Number: 274066-004US
Intel® 80332 I/O Processor Datasheet
Tables
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Pin Description Nomenclature.............................................................................15
DDR SDRAM Signals..........................................................................................16
MISC SDRAM Signals.........................................................................................17
DDR-II SDRAM Signals.......................................................................................17
Peripheral Bus Interface Signals .........................................................................18
PCI Express Signals............................................................................................19
B PCI (Slot Expansion) Bus Signals....................................................................20
A PCI (IOP) Bus Signals .....................................................................................22
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C/SMBus Signals ..............................................................................................24
Interrupt Signals ..................................................................................................24
Hot-Plug Controller Signals for Parallel 1-slot, no-glue .......................................25
UART Signals......................................................................................................26
Test and Miscellaneous Signals..........................................................................28
Reset Strap Signals.............................................................................................29
Power and Ground Pins ......................................................................................31
Pin Mode Behavior ..............................................................................................32
Pin Multiplexing for Functional Modes.................................................................35
FC-style, H-PBGA Package Dimensions ............................................................36
829-Lead Package - Alphabetical Ball Listings ...................................................40
829-Lead Package - Alphabetical Signal Listings ...............................................48
Absolute Maximum Ratings.................................................................................57
Operating Conditions...........................................................................................57
DC Characteristics ..............................................................................................58
I
CC
Characteristics ..............................................................................................59
PCI Clock Timings...............................................................................................60
DDR Clock Timings .............................................................................................60
PCI Express Clock Timings.................................................................................61
DDR SDRAM Signal Timings ..............................................................................62
DDR-II SDRAM Signal Timings...........................................................................63
Peripheral Bus Signal Timings ............................................................................64
PCI Signal Timings..............................................................................................65
I
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C/SMBus Signal Timings ..................................................................................66
UART Signal Timings ..........................................................................................66
PCI Express Tx Output Specifications ................................................................67
PCI Express Rx Input Specifications...................................................................68
Boundary Scan Test Signal Timings ...................................................................69
AC Measurement Conditions ..............................................................................74
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