PRELIMINARY
RX62N Group, RX621 Group
Renesas 32-Bit MCU
REJ03B0281-0050
Rev.0.50
Mar. 11, 2010
1.
1.1
Overview
Features
The RX62N/RX621 Group is a set of MCUs that feature the high-speed, high-performance RX CPU as the processor
core.
Each basic instruction is executable in one cycle of the system clock. Calculation functionality is enhanced by the
inclusion of a single-precision floating-point calculation unit as well as a 32-bit multiplier and divider. Additionally, code
efficiency is improved by instructions with lengths that are variable in byte units to cover an enhanced range of
addressing modes.
Timers, an Ethernet controller, USB 2.0 host/function modules, serial communications interfaces, I
2
C bus interfaces,
CAN modules, an A/D converter, and a D/A converter are incorporated as peripheral functions which are essential to
embedded network devices.
Facilities for connecting external memory are also included, enabling direct connection to memory and peripheral LSI
circuits. Large-capacity flash memory units capable of high-speed operation are included as on-chip memory,
significantly reducing the cost of configuring systems.
1.1.1
Applications
Industrial equipment and embedded network devices
Notes to users:
• While the information contained herein is believed to be accurate, it may contain technical
inaccuracies or typographical errors.
• The specification may be subject to change due to produce improvements or other reasons.
Please verify the document is the latest version available.
REJ03B0281-0050 Rev.0.50
Page 1 of 101
Mar. 11, 2010
Under development
Preliminary Specification
Specifications in this preliminary version are subject to change.
RX62N Group, RX621 Group
1.1.2
Outline of Specifications
1. Overview
Table 1.1 lists the specifications in outline, and table 1.2 lists the functions of products.
Table 1.1
CPU
Outline of Specifications
Module/Function
CPU
Classification
Description
•
Maximum operating frequency: 100 MHz
•
32-bit RX CPU
•
Minimum instruction execution time: One instruction per state (cycle of the system clock)
•
Address space: 4-Gbyte linear
•
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
•
Basic instructions: 73
•
Floating-point instructions: 8
•
DSP instructions: 9
•
Addressing modes: 10
•
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
•
On-chip 32-bit multiplier: 32 x 32
→
64 bits
•
On-chip divider: 32 / 32
→
32 bits
•
Barrel shifter: 32 bits
•
Memory-protection unit (MPU) (as an optional function)*
1
FPU
•
Single precision (32-bit) floating point
•
Data types and floating-point exceptions in conformance with the IEEE754 standard
Memory
ROM
•
ROM capacity: 512 Kbytes (max.)
•
Two on-board programming modes
Boot mode (The user MAT is programmable via the SCI and USB.)
User program mode
•
Parallel programmer mode (for off-board programming)
RAM
Data flash
MCU operating modes
RAM capacity: 96 Kbytes (max.)
Data flash capacity: 32 Kbytes
Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled
expansion mode (software switching)
REJ03B0281-0050 Rev.0.50
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Mar. 11, 2010
Under development
Preliminary Specification
Specifications in this preliminary version are subject to change.
RX62N Group, RX621 Group
Classification
Clock
1. Overview
Module/Function
Clock generation
circuit
Description
•
Two circuits: Main clock oscillator and subclock oscillator
•
Internal oscillator: Low-speed on-chip oscillator
•
Structure of a PLL frequency synthesizer and frequency divider for selectable operating
frequency
•
Oscillation stoppage detection
•
Independent frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLK), and external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system
clock (ICLK): 8 to 100 MHz
Peripheral modules run in synchronization with the peripheral module
clock (PCLK): 8 to 50 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK): 8 to 50 MHz
Reset
Pin reset, power-on reset, voltage-monitoring reset, watchdog timer reset, independent
watchdog timer reset, and deep software standby reset
Voltage detection circuit
When the voltage on VCC falls below the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.
Low power
consumption
Low power
consumption facilities
•
Module stop function
•
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Interrupt
Interrupt control unit
•
Peripheral function interrupts: 146 sources
•
External interrupts: 16 (pins IRQ0 to IRQ15)
•
Non-maskable interrupts: 3 (the NMI pin, oscillation stop detection interrupt, and
voltage-monitoring interrupt)
•
Sixteen levels specifiable for the order of priority
User break controller
(as an optional
function)
External bus extension
•
Two breakpoint channels
•
Address breaks in fetch cycles are specifiable (enabling ROM correction)
•
The external address space can be divided into nine areas (CS0 to CS7, SDCS), each
with independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7), 128 Mbytes (SDCS)
A chip-select signal (CS0# to CS7#, SDCS#) can be output for each area.
Each area is specifiable as an 8-, 16-, or 32-bit bus space (however, only 176-pin
versions support 32-bit bus spaces).
The data arrangement in each area is selectable as little or big endian (only for data).
•
SDRAM interface connectable
•
Bus format: Separate buses
•
Wait control
•
Write buffer facility
REJ03B0281-0050 Rev.0.50
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Mar. 11, 2010
Under development
Preliminary Specification
Specifications in this preliminary version are subject to change.
RX62N Group, RX621 Group
Classification
DMA
1. Overview
Module/Function
DMA controller
Description
•
4 channels
•
Three transfer modes: Normal transfer, repeat transfer, and block transfer
•
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
EXDMA controller
•
2 channels
•
Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster transfer
•
Single-address transfer enabled with the EDACK signal
•
Capable of direct data transfer to TFT LCD panels
•
Activation sources: Software trigger, external DMA requests (EDREQ), and interrupt
requests from peripheral functions
Data transfer
controller
•
Three transfer modes: Normal transfer, repeat transfer, and block transfer
•
Activation sources: Software trigger, external interrupts and interrupt requests from
peripheral functions
I/O ports
Programmable I/O
ports
I/O ports for the 176-pin LFBGA/145-pin TFLGA/144-pin LQFP/100-pin LQFP/85-pin TFLGA
•
I/O pins: 126/103/103/72/58
•
Input pins: 2/2/2/2/2
•
Pull-up resistors: 56/44/44/40/28
•
Open-drain outputs: 35/33/33/27/23
•
5-V tolerance: 11/11/11/7/6
Timers
Multi-function timer
pulse unit
•
(16 bits x 6 channels) x 2 units
•
Time bases for the 12 16-bit timer channels can be provided via up to 32
pulse-input/output lines and six pulse-input lines
•
Select from among eight counter-input clock signals for each channel (MPCLK/1,
MPCLK/4, MPCLK/16, MPCLK/64, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
•
Input capture function
•
21 output compare/input capture registers
•
Pulse output mode
•
Complementary PWM output mode
•
Reset synchronous PWM mode
•
Phase-counting mode
•
Generation of triggers for A/D converter conversion
Port output enable
Controls the high-impedance state of the MTU’s waveform output pins
REJ03B0281-0050 Rev.0.50
Page 4 of 101
Mar. 11, 2010
Under development
Preliminary Specification
Specifications in this preliminary version are subject to change.
RX62N Group, RX621 Group
Classification
Timers
1. Overview
Module/Function
Programmable pulse
generator
Description
•
(4 bits x 4 groups) x 2 units
•
Pulse output with the MTU output as a trigger
•
Maximum of 32-bit pulse output possible
8-bit timers
•
(8 bits x 2 channels) x 2 units
•
Select from among seven internal clock signals (PCLK, PCLK/2, PCLK/8, PCLK/32,
PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal
•
Capable of output of pulse trains with desired duty cycles or of PWM signals
•
The 2 channels of each unit can be cascaded to create a 16-bit timer
•
Generation of triggers for A/D converter conversion
•
Capable of generating baud-rate clocks for SCI5 and SCI6
Compare match timer
•
(16 bits x 2 channels) x 2 units
•
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Watchdog timer
•
8 bits x 1 channel
•
Select from among eight counter-input clock signals (PCLK/4, PCLK/64, PCLK/128,
PCLK/512, PCLK/2048, PCLK/8192, PCLK/32768, PCLK/131072)
•
Switchable between watchdog timer mode and interval timer mode
Independent
watchdog timer
Realtime clock
•
14 bits x 1 channel
•
Counter-input clock: Dedicated on-chip oscillator
•
Clock source: Subclock
•
Time/calendar
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Communication
function
Ethernet controller
•
Input and output of Ethernet/IEEE 802.3 frames
•
Transfer at 10 or 100 Mbps
•
Full- and half-duplex modes
•
MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as
defined in IEEE 802.3u
•
Detection of Magic Packets
TM
*
or output of a "wake-on-LAN" signal (WOL)
•
Compliance with flow control as defined in IEEE 802.3x standards
Note:
*
Magic Packet
DMA controller for
Ethernet controller
USB 2.0
host/function module
TM
is a registered trademark of Advanced Micro Devices, Inc.
•
Alleviation of CPU loads by the descriptor control method
•
Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes
•
Includes a UDC (USB Device Controller) and transceiver for USB 2.0
•
Single port (176-pin products: two ports)
•
Compliance with the USB 2.0 specification
•
Transfer rate: Full speed (12 Mbps)
•
Self-power mode and bus power are selectable
•
OTG (On the Go) operation is possible
•
Incorporates 2 Kbytes of RAM as a transfer buffer
Serial
communications
interfaces
•
6 channels
•
Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
•
Multi-processor communications function
•
On-chip baud rate generator allows selection of the desired bit rate
•
Choice of LSB-first or MSB-first transfer
•
Average transfer rate clock can be input from TMR timers for SCI5 and SCI6
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Mar. 11, 2010
