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RFD16N05LSM_NL

16A, 50V, 0.056ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252AA, LEAD FREE PACKAGE-3

器件类别:分立半导体    晶体管   

厂商名称:Rochester Electronics

厂商官网:https://www.rocelec.com/

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器件参数
参数名称
属性值
厂商名称
Rochester Electronics
零件包装代码
TO-252AA
包装说明
LEAD FREE PACKAGE-3
针数
4
Reach Compliance Code
unknown
其他特性
MEGAFET
外壳连接
DRAIN
配置
SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压
50 V
最大漏极电流 (ID)
16 A
最大漏源导通电阻
0.056 Ω
FET 技术
METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码
TO-252AA
JESD-30 代码
R-PSSO-G2
元件数量
1
端子数量
2
工作模式
ENHANCEMENT MODE
封装主体材料
PLASTIC/EPOXY
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
极性/信道类型
N-CHANNEL
最大脉冲漏极电流 (IDM)
45 A
认证状态
COMMERCIAL
表面贴装
YES
端子面层
MATTE TIN
端子形式
GULL WING
端子位置
SINGLE
晶体管应用
SWITCHING
晶体管元件材料
SILICON
文档预览
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RFD16N05L, RFD16N05LSM
Data Sheet
December 2003
16A, 50V, 0.047 Ohm, Logic Level,
N-Channel Power MOSFETs
These are N-Channel logic level power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI
integrated circuits gives optimum utilization of silicon,
resulting in outstanding performance. They were designed
for use with logic level (5V) driving sources in applications
such as programmable controllers, automotive switching,
switching regulators, switching converters, motor relay
drivers and emitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate biases
in the 3V to 5V range, thereby facilitating true on-off power
control directly from logic circuit supply voltages.
Formerly developmental type TA09871.
Features
• 16A, 50V
• r
DS(ON)
= 0.047Ω
• UIS SOA Rating Curve (Single Pulse)
• Design Optimized for 5V Gate Drives
• Can be Driven Directly from CMOS, NMOS, TTL Circuits
• Compatible with Automotive Drive Requirements
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Majority Carrier Device
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
PART NUMBER
RFD16N05L
RFD16N05LSM
PACKAGE
TO-251AA
TO-252AA
BRAND
RFD16N05L
RFD16N05LSM
Symbol
D
NOTE: When ordering, include the entire part number. Add the suffix 9A
to obtain the TO-252AA variant in tape and reel, i.e. RFD16N05LSM9A
G
S
Packaging
JEDEC TO-251AA
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
©2003 Fairchild Semiconductor Corporation
RFD16N05L, RFD16N05LSM Rev. B1
RFD16N05L, RFD16N05LSM
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFD16N05L,
RFD16N05LSM
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
50
50
16
45
±10
60
0.48
-55 to 150
300
260
UNITS
V
V
A
A
V
W
W/
o
C
o
C
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
DSS
TEST CONDITIONS
I
D
= 250mA, V
GS
= 0V, Figure 10
V
GS
= V
DS
, I
D
= 250mA, Figure 9
V
DS
= 40V, V
GS
= 0V
T
C
= 150
o
C
MIN
50
1
-
-
-
-
-
-
-
-
-
-
-
V
GS
= 0V to 10V
V
GS
= 0V to 5V
V
GS
= 0V to 1V
V
DD
= 40V,
I
D
= 16A,
R
L
= 2.5Ω
Figures 17, 18
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
14
30
42
14
-
-
-
-
-
-
MAX
-
2
1
50
100
0.047
0.056
60
-
-
-
-
100
80
45
3
2.083
100
UNITS
V
V
µA
µA
nA
ns
ns
ns
ns
ns
ns
nC
nC
nC
o
C/W
o
C/W
Drain to Source Breakdown Voltage
Gate to Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
I
GSS
r
DS(ON)
V
GS
=
±10V,
V
DS
= 0V
I
D
= 16A, V
GS
= 5V
I
D
= 16A, V
GS
= 4V
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
t
(ON)
t
d(ON)
t
r
t
d(OFF)
t
f
t
(OFF)
Q
g(TOT)
Q
g(5)
Q
g(TH)
R
θJC
R
θJA
V
DD
= 25V, I
D
= 8A,
V
GS =
5V, R
GS
= 12.5Ω
Figures 15, 16
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Diode Reverse Recovery Time
NOTES:
2. Pulse Test: Pulse Width
300ms, Duty Cycle
2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature.
SYMBOL
V
SD
t
rr
I
SD
= 16A
I
SD
= 16A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
TYP
-
-
MAX
1.5
125
UNITS
V
ns
©2003 Fairchild Semiconductor Corporation
RFD16N05L, RFD16N05LSM Rev. B1
RFD16N05L, RFD16N05LSM
Typical Performance Curves
Unless Otherwise Specified
1.2
POWER DISSIPATION MULTIPLIER
1.0
I
D
, DRAIN CURRENT (A)
0
25
50
75
100
T
C
, CASE TEMPERATURE (
o
C)
125
150
15
0.8
20
0.6
0.4
10
5
0.2
0
0
25
50
75
100
125
T
C
, CASE TEMPERATURE (
o
C)
150
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
10
2
I
AS
, AVALANCHE CURRENT (A)
T
C
= 25
o
C
T
J
= MAX RATED
I
D
MAX CONTINUOUS
10
2
Idm
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
I
D
, DRAIN CURRENT (A)
10
OPERATION IN THIS AREA
LIMITED BY r
DS(ON)
1
DC
10
If R = 0
t
AV
= (L)(I
AS
)/(1.3 RATED BV
DSS
- V
DD
)
1
0.01
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3 RATED BV
DSS
- V
DD
) +1]
0.10
1
t
AV
, TIME IN AVALANCHE (ms)
10
0.1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10
2
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA
(SINGLE PULSE UIS SOA)
45
I
DS
, DRAIN TO SOURCE CURRENT (A)
V
GS
= 10V
V
GS
= 4V
V
GS
= 5V
30
I
DS(ON)
, DRAIN TO SOURCE ON CURRENT (A)
T
C
= 25
o
C
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
45
V
DS
= 15V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
30
V
GS
= 3V
15
15
V
GS
= 2V
0
0
1.5
3.0
4.5
6.0
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
7.5
0
0
1.5
3.0
4.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
6.0
FIGURE 5. SATURATION CHARACTERISTICS
FIGURE 6. TRANSFER CHARACTERISTICS
©2003 Fairchild Semiconductor Corporation
RFD16N05L, RFD16N05LSM Rev. B1
RFD16N05L, RFD16N05LSM
Typical Performance Curves
Unless Otherwise Specified
(Continued)
1.4
V
DS
= 15V
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
4
5
6
7
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
= 16V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
2.5
I
D
= 16A
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
1.5
1.0
0.5
0
-50
0
50
100
150
200
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.4
1.3
NORMALIZED GATE
THRESHOLD VOLTAGE
1.2
1.1
1.0
0.9
0.8
0.7
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
I
D
= 250µA
V
GS
= V
DS
1.4
I
D
= 250µA
1.2
1.0
0.8
0.6
0.6
-50
0
50
100
150
200
0
-50
0
50
100
150
200
T
J
, JUNCTION TEMPERATURE (
o
C)
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 9. NORMALIZED GATE THRESHOLD vs JUNCTION
TEMPERATURE
2000
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1600
C, CAPACITANCE (pF)
C
ISS
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
C
DS
+ C
GD
C
OSS
C
RSS
0
0
5
10
15
20
25
37.5
8
1200
6
25
800
GATE
SOURCE
VOLTAGE
4
12.5
2
DRAIN SOURCE VOLTAGE
0
I G
(
REF
)
20 ------------------------
-
I G
(
ACT
)
t, TIME (µs)
I G
(
REF
)
-
80 ------------------------
I G
(
ACT
)
0
400
V
DS,
DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
©2003 Fairchild Semiconductor Corporation
RFD16N05L, RFD16N05LSM Rev. B1
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
GS
= 0V
f = 1MHz
50
10
R
L
= 3.125Ω, V
GS
= 5V
I
G(REF)
= 0.60mA
PLATEAU VOLTAGES IN
DESCENDING ORDER:
V
DD
= BV
DSS
V
= 0.75 BV
V
DD
= BV
DSS
V
DD
= 0.50 BV
DSS
V
DD
= BV
DSS
DD
DSS
V
DD
= 0.25 BV
DSS
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