RFG50N05L, RFP50N05L
Data Sheet
January 2002
50A, 50V, 0.022 Ohm, Logic Level,
N-Channel Power MOSFETs
These are logic-level N-channel power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI
integrated circuits gives optimum utilization of silicon,
resulting in outstanding performance. They were designed
for use with logic-level (5V) driving sources in applications
such as programmable controllers, automotive switching,
switching regulators, switching converters, motor relay
drivers and emitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate bias in
the 3V - 5V range, thereby facilitating true on-off power
control directly from integrated circuit supply voltages.
Formerly developmental type TA09872.
Features
• 50A, 50V
• r
DS(ON)
= 0.022
Ω
• UIS SOA Rating Curve (Single Pulse)
• Design Optimized for 5V Gate Drive
• Can be Driven Directly from CMOS, NMOS, TTL Circuits
• Compatible with Automotive Drive Requirements
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Majority Carrier Device
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
PART NUMBER
RFG50N05L
RFP50N05L
PACKAGE
TO-247
TO-220AB
BRAND
RFG50N05L
RFP50N05L
Symbol
D
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in the tape and reel, i.e., RFP50N05L9A.
G
S
Packaging
JEDEC STYLE TO-247
SOURCE
DRAIN
GATE
DRAIN
(BOTTOM
SIDE METAL)
DRAIN (FLANGE)
JEDEC TO-220AB
SOURCE
DRAIN
GATE
©2002 Fairchild Semiconductor Corporation
RFG50N05L, RFP50N05L Rev. B
RFG50N05L, RFP50N05L
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFG50N05L
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
Drain to Gate Voltage (R
GS
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Above T
C
= 25
o
C, Derate Linearly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
50
50
50
130
±
10
110
0.88
RFP50N05L
50
50
50
130
±
10
110
0.88
UNITS
V
V
A
A
V
W
W/
o
C
-
o
C
o
C
o
C
Refer to UIS SOA Curve
-55 to 150
300
260
-55 to 150
300
260
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
DSS
TEST CONDITIONS
I
D
= 250
µ
A, V
GS
= 0V (Figure 10)
V
GS
= V
DS
, I
D
= 250
µ
A (Figure 9)
V
DS
= Rated BV
DSS
, V
GS
= 0
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0, T
C
= 150
o
C
MIN
50
1
-
-
-
-
-
-
-
-
-
-
-
V
GS
= 0 to 10V
V
GS
= 0 to 5V
V
GS
= 0 to 1V
V
DD
= 40V, I
D
= 50A
R
L
= 0.8
Ω
(Figures 17, 18)
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
15
50
50
15
-
-
-
-
-
-
MAX
-
2
25
250
±
100
0.022
0.027
100
-
-
-
-
100
140
80
6
1.14
80
UNITS
V
V
µ
A
µ
A
nA
Ω
Ω
ns
ns
ns
ns
ns
ns
nC
nC
nC
o
C/W
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
I
GSS
r
DS(ON)
V
GS
=
±
10V, V
DS
= 0V
I
D
= 50A, V
GS
= 5V (Figure 7)
I
D
= 50A, V
GS
= 4V
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
t
(ON)
t
D(ON)
t
r
t
D(OFF)
t
f
t
(OFF)
Q
G(TOT)
Q
G(5)
Q
G(th
)
R
θ
JC
R
θ
JA
V
GS
= 5V, R
GS
= 2.5
Ω
, R
L
= 1
Ω
(Figures 12, 15, 16)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage (Note 2)
Diode Reverse Recovery Time
NOTES:
2. Pulsed: pulse duration = 300
µ
s maximum, duty cycle = 2%.
3. Repititive rating: pulse width limited by maximum junction temperature.
©2002 Fairchild Semiconductor Corporation
RFG50N05L, RFP50N05L Rev. B
SYMBOL
V
SD
t
rr
I
SD
= 50A
TEST CONDITIONS
MIN
-
-
TYP
-
-
MAX
1.5
1.25
UNITS
V
ns
I
SD
= 50A, dI
SD
/dt = 100A/
µ
s
RFG50N05L, RFP50N05L
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
T
C
, CASE TEMPERATURE (
o
C)
I
D
, DRAIN CURRENT (A)
50
40
30
20
10
0
25
50
75
100
125
150
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
100
I
DS
, DRAIN TO SOURCE CURRENT (A)
I
D
MAX CONTINUOUS
DC OPERATION
10
OPERATION IN THIS
AREA LIMITED
BY r
DS(ON)
1
I
AS
, AVALANCHE CURRENT (A)
T
C
= 25
o
C
T
J
= MAX RATED
1000
IF R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
IF R = 0
T
AV
= (L/R) IN [(I
AS
*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
I
DM
100
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
0.1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
100
10
0.01
0.1
1
10
t
AV
, TIME IN AVALANCHE (ms)
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SAFE
OPERATING AREA
I
D(ON)
, DRAIN TO SOURCE CURRENT (A)
140
I
DS
, DRAIN TO SOURCE CURRENT (A)
120
100
80
60
40
20
V
GS
= 2V
0
0
1.5
3.0
4.5
6.0
7.5
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 3V
V
GS
= 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
T
C
- 25
o
C
V
GS
= 5V
140
120
100
V
DS
= 15V
80
60
40
20
0
0
1.5
3.0
4.5
6.0
7.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
-55
o
C
25
o
C
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
T
C
- 25
o
C
150
o
C
V
GS
= 4V
FIGURE 5. SATURATION CHARACTERISTICS
FIGURE 6. TRANSFER CHARACTERISTICS
©2002 Fairchild Semiconductor Corporation
RFG50N05L, RFP50N05L Rev. B
RFG50N05L, RFP50N05L
Typical Performance Curves
3.0
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
2.5
2.0
1.5
1.0
0.5
0
-50
0
50
100
150
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
V
GS
= 5V
I
D
= 50A
(Continued)
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
I
D
= 50A, V
GS
= 5V
1.5
1.2
0.8
0.4
0
4
5
6
V
GS
, GATE TO SOURCE VOLTAGE (V)
7
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2.0
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs GATE VOLTAGE
2.0
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
V
GS
= V
DS
, I
D
= 250µA
1.8
NORMALIZED GATE
THRESHOLD VOLTAGE
I
D
= 250µA
1.8
1.2
1.2
0.8
0.8
0.4
0.4
0
-50
0
50
100
T
J
, JUNCTION TEMPERATURE (
o
C)
150
0
-50
0
50
100
150
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
50
R
L
= 0Ω
I
G(REF)
= 1.25mA
37.5
V
DD
= BV
DSS
25
0.75BV
DSS
V
DD
= BV
DSS
0.75BV
DSS
GATE TO
SOURCE
VOLTAGE
0.50BV
DSS
5
10
GATE TO SOURCE VOLTAGE (V)
6000
5000
C, CAPACITANCE (pF)
4000
3000
2000
C
OSS
1000
C
RSS
0
0
5
10
15
20
25
V
DS
, DRAIN TO SOURCE (V)
DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
≈
C
DS
+ C
GD
C
ISS
12.5
0.50BV
DSS
0.25BV
DSS
0.25BV
DSS
DRAIN TO SOURCE VOLTAGE
0
20
I
G(REF)
I
G(ACT)
TIME-MICROSECONDS
80
I
G(REF)
I
G(ACT)
0
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
©2002 Fairchild Semiconductor Corporation
RFG50N05L, RFP50N05L Rev. B
RFG50N05L, RFP50N05L
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
DUT
t
P
R
G
-
I
AS
V
DD
t
P
V
DS
V
DD
+
0V
I
AS
0.01Ω
0
t
AV
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
t
ON
V
DS
V
DS
V
GS
R
L
+
t
OFF
t
d(OFF)
t
r
t
f
90%
t
d(ON)
90%
DUT
R
GS
V
GS
-
V
DD
0
10%
90%
10%
V
GS
0
10%
50%
PULSE WIDTH
50%
FIGURE 15. SWITCHING TIME TEST CIRCUIT
FIGURE 16. RESISTIVE SWITCHING WAVEFORMS
V
DS
R
L
V
DD
V
DS
V
GS
= 10V
V
GS
+
Q
g(TOT)
Q
g(5)
V
DD
V
GS
V
GS
= 1V
0
Q
g(TH)
I
G(REF)
0
V
GS
= 5V
-
DUT
I
G(REF)
FIGURE 17. GATE CHARGE TEST CIRCUIT
FIGURE 18. GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFG50N05L, RFP50N05L Rev. B
