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RFL1N10L

Power Field-Effect Transistor, 1A I(D), 100V, 1.2ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF,

器件类别:分立半导体    晶体管   

厂商名称:Fairchild

厂商官网:http://www.fairchildsemi.com/

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器件参数
参数名称
属性值
是否Rohs认证
不符合
Reach Compliance Code
unknown
ECCN代码
EAR99
Is Samacsys
N
外壳连接
DRAIN
配置
SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压
100 V
最大漏极电流 (Abs) (ID)
1 A
最大漏极电流 (ID)
1 A
最大漏源导通电阻
1.2 Ω
FET 技术
METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码
TO-205AF
JESD-30 代码
O-MBCY-W3
JESD-609代码
e0
元件数量
1
端子数量
3
工作模式
ENHANCEMENT MODE
最高工作温度
150 °C
封装主体材料
METAL
封装形状
ROUND
封装形式
CYLINDRICAL
峰值回流温度(摄氏度)
NOT SPECIFIED
极性/信道类型
N-CHANNEL
最大功率耗散 (Abs)
8.33 W
最大脉冲漏极电流 (IDM)
5 A
认证状态
Not Qualified
表面贴装
NO
端子面层
Tin/Lead (Sn/Pb)
端子形式
WIRE
端子位置
BOTTOM
处于峰值回流温度下的最长时间
NOT SPECIFIED
晶体管应用
SWITCHING
晶体管元件材料
SILICON
Base Number Matches
1
文档预览
RFL1N10L
August 1999
1A, 100V, 1.200 Ohm, Logic Level, N-Channel
Power MOSFET
Description
This is an N-Channel enhancement mode silicon gate power
field effect transistor specifically designed for use with logic
level (5V) driving sources in applications such as program-
mable controllers, automotive switching, and solenoid driv-
ers. This performance is accomplished through a special
gate oxide design which provides full rated conduction at
gate biases in the 3V to 5V range, thereby facilitating true
on-off power control directly from logic circuit supply volt-
ages.
Formerly developmental type TA09524.
Features
• 1A, 100V
• r
DS(ON)
= 1.200
Ordering Information
PART NUMBER
RFL1N10L
PACKAGE
TO-205AF
BRAND
RFL1N10L
NOTE: When ordering, use the entire part number.
Symbol
D
G
S
Packaging
JEDEC TO-205AF
DRAIN
(CASE)
GATE
SOURCE
©2001 Fairchild Semiconductor Corporation
RFL1N10L Rev. A
RFL1N10L
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFL1N10L
100
100
1
5
±
10
8.33
0.0667
-55 to 150
260
UNITS
V
V
A
A
V
W
W/
o
C
o
C
o
C
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
Drain to Gate Voltage (R
GS
= 1M
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
Gate to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Above T
C
= 25
o
C, Derate Linearly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . .T
L
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
DSS
TEST CONDITIONS
I
D
= 250
µ
A, V
GS
= 0
V
GS
= V
DS
, I
D
= 250
µ
A
V
DS
= Rated BV
DSS
V
DS
= 0.8 x Rated BV
DSS
, V
DS
= 80V,
T
C
= 125
o
C
MIN
100
1
-
-
-
-
-
-
-
-
-
V
GS
= 0V, V
DS
= 25V, f = 1MHz
(Figure 9)
-
-
-
-
TYP
-
-
-
-
-
-
-
10
15
25
30
-
-
-
-
MAX
-
2
1
25
±
100
1.200
1.2
25
45
45
50
200
80
35
15
UNITS
V
V
µ
A
µ
A
nA
V
ns
ns
ns
ns
pF
pF
pF
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
Drain to Source On Voltage (Note 2)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
I
GSS
r
DS(ON)
V
DS(ON)
t
d(ON)
t
r
t
d(OFF)
t
f
C
ISS
C
OSS
C
RSS
R
θ
JC
V
GS
=
±
10V, V
DS
= 0
I
D
= 1A, V
GS
= 5V (Figures 6, 7)
I
D
= 1A, V
GS
= 5V
I
D
1A, V
DD
= 50V, R
G
= 6.25
,
V
GS
= 5V, R
L
= 50
(Figures 10, 11, 12)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage (Note 2)
Diode Reverse Recovery Time
NOTES:
2. Pulse test: width
300
µ
s duty cycle
2%.
3. Repetitive rating: pulse witdh limited by maximum junction temperature.
SYMBOL
V
SD
t
rr
TEST CONDITIONS
I
SD
= 1A
I
SD
= 2A, dI
SD
/dt = 50A/
µ
s
MIN
-
-
TYP
-
100
MAX
1.4
-
UNITS
V
ns
©2001 Fairchild Semiconductor Corporation
RFL1N10L Rev. A
RFL1N10L
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
Unless Otherwise Specified
1.2
1.0
I
D
, DRAIN CURRENT (A)
0
25
50
75
100
T
C
, CASE TEMPERATURE (
o
C)
125
150
0.8
0.6
0.4
0.2
0
25
1.0
0.8
0.6
0.4
0.2
0
50
75
100
125
T
C
, CASE TEMPERATURE (
o
C)
150
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
I
DS,
DRAIN TO SOURCE CURRENT (A)
10
OPERATION IN THIS AREA
MAY BE LIMITED BY r
DS(ON)
I
D
, DRAIN CURRENT (A)
1
T
C
= 25
o
C
8
7
6
5
4
3
2
V
GS
= 3V
1
V
GS
= 2V
V
GS
= 4V
V
GS
= 5V
PULSE DURATION = 80µs
DUTY CYCLE
2%
T
C
= 25
o
C
V
GS
= 10V
0.1
0.01
0
1
10
100
V
DS
, DRAIN TO SOURCE (V)
1000
0
1
2
3
4
5
6
7
8
9
10
V
DS,
DRAIN TO SOURCE VOLTAGE (V)
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. SATURATION CHARACTERISTICS
6
5
4
V
DS
= 10V
PULSE DURATION = 80µs
DUTY CYCLE
2%
-40
o
C
25
o
C
r
DS(ON),
DRAIN TO SOURCE ON
RESISTANCE (Ω)
2
I
D(ON),
DRAIN CURRENT (A)
1.5
125
o
C
V
GS
= 5V
PULSE DURATION = 80µs
DUTY CYCLE
2%
125
o
C
3
2
125
o
C
1
-40
o
C
0
1
2
5
3
4
V
GS,
GATE TO SOURCE VOLTAGE (V)
6
1
25
o
C
-40
o
C
0.5
0
0
1
2
3
4
5
I
D,
DRAIN CURRENT (A)
6
7
FIGURE 5. TRANSFER CHARACTERISTICS
FIGURE 6. DRAIN TO SOURCE ON RESISTANCE vs DRAIN
CURRENT
©2001 Fairchild Semiconductor Corporation
RFL1N10L Rev. A
RFL1N10L
Typical Performance Curves
2.5
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
I
D
= 1A
V
GS
= 5V
THRESHOLD VOLTAGE
2
NORMALIZED GATE
1.5
Unless Otherwise Specified
(Continued)
2
V
GS
= V
DS
I
D
= 250µA
1.5
1
1
0.5
0.5
-50
0
50
100
T
J,
JUNCTION TEMPERATURE (
o
C)
150
-50
0
50
100
T
J,
JUNCTION TEMPERATURE (
o
C)
150
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
240
200
C, CAPACITANCE (pF)
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
BV
DSS
R
L
= 50Ω
I
G(REF)
= 0.094mA
V
GS
= 5V
V
DD
= V
DSS
V
DD
= V
DSS
4
8
f = 1MHz
75
160
120
C
ISS
80
C
OSS
40
C
RSS
0
10
20
30
40
50
V
DS,
DRAIN TO SOURCE VOLTAGE (V)
60
6
50
25
GATE
SOURCE
VOLTAGE
0.75V
DSS
0.75V
DSS
0.50V
DSS
0.50V
DSS
0.25V
DSS
0.25V
DSS
DRAIN SOURCE VOLTAGE
I
20
G(REF)
I
G(ACT)
I
80
G(REF)
I
G(ACT)
2
0
t, TIME (µs)
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 10. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
RFL1N10L Rev. A
Test Circuits and Waveforms
t
ON
t
d(ON)
t
r
R
L
V
DS
+
t
OFF
t
d(OFF)
t
f
90%
90%
R
G
DUT
-
V
DD
0
10%
90%
10%
V
GS
V
GS
0
10%
50%
PULSE WIDTH
50%
FIGURE 11. SWITCHING TIME TEST CIRCUIT
FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
©2001 Fairchild Semiconductor Corporation
RFL1N10L Rev. A
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