RFG50N06, RFP50N06, RF1S50N06SM
Data Sheet
January 2002
50A, 60V, 0.022 Ohm, N-Channel Power
MOSFETs
These N-Channel power MOSFETs are manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relay drivers. These transistors can be operated
directly from integrated circuits.
Formerly developmental type TA49018.
Features
• 50A, 60V
• r
DS(ON)
= 0.022
Ω
• Temperature Compensating PSPICE
®
Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175
o
C Operating Temperature
Symbol
D
Ordering Information
PART NUMBER
RFG50N06
RFP50N06
RF1S50N06SM
PACKAGE
TO-247
TO-220AB
TO-263AB
BRAND
RFG50N06
RFP50N06
F1S50N06
S
G
NOTE: When ordering, use the entire part number. Add the suffix, 9A,
to obtain the TO-263AB variant in tape and reel, i.e. RF1S50N06SM9A.
Packaging
JEDEC STYLE TO-247
SOURCE
DRAIN
GATE
DRAIN
(BOTTOM
SIDE METAL)
DRAIN
(FLANGE)
JEDEC TO-220AB
SOURCE
DRAIN
GATE
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
©2002 Fairchild Semiconductor Corporation
RFG50N06, RFP50N06, RF1S50N06SM Rev. B
RFG50N06, RFP50N06, RF1S50N06SM
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFG50N06, RFP50N06
RF1S50N06SM
60
60
±
20
50
(Figure 5)
(Figure 6)
131
0.877
-55 to 175
300
260
UNITS
V
V
V
A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
Drain to Gate Voltage (R
GS
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg
W
W/
o
C
o
C
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
DSS
TEST CONDITIONS
I
D
= 250
µ
A, V
GS
= 0V (Figure 11)
V
GS
= V
DS
, I
D
= 250
µ
A (Figure 10)
V
DS
= 60V,
V
GS
= 0V
V
GS
=
±
20V
I
D
= 50A, V
GS
= 10V (Figures 9)
V
DD
= 30V, I
D
= 50A
R
L
= 0.6
Ω
, V
GS
= 10V
R
GS
= 3.6
Ω
(Figure 13)
T
C
= 25
o
C
T
C
= 150
o
C
MIN
60
2
-
-
-
-
-
-
-
-
-
-
V
GS
= 0 to 20V
V
GS
= 0 to 10V
V
GS
= 0 to 2V
V
DD
= 48V, I
D
= 50A,
R
L
= 0.96
Ω
I
g(REF)
= 1.45mA
(Figure 13)
-
-
-
-
-
-
(Figure 3)
TO-247
TO-220, TO-263
-
-
-
TYP
-
-
-
-
-
-
-
12
55
37
13
-
125
67
3.7
2020
600
200
-
-
-
MAX
-
4
1
50
±
100
0.022
95
-
-
-
-
75
150
80
4.5
-
-
-
1.14
30
62
UNITS
V
V
µ
A
µ
A
nA
Ω
ns
ns
ns
ns
ns
ns
nC
nC
nC
pF
pF
pF
o
C/W
o
C/W
o
C/W
Drain to Source Breakdown Voltage
Gate to Source Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
I
GSS
r
DS(ON)
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Q
g(TOT)
Q
g(10)
Q
g(TH)
C
ISS
C
OSS
C
RSS
R
θ
JC
R
θ
JA
V
DS
= 25V, V
GS
= 0V
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
V
SD
t
rr
I
SD
= 50A
I
SD
= 50A, dI
SD
/dt = 100A/
µ
s
TEST CONDITIONS
MIN
-
-
TYP
-
-
MAX
1.5
125
UNITS
V
ns
©2002 Fairchild Semiconductor Corporation
RFG50N06, RFP50N06, RF1S50N06SM Rev. B
RFG50N06, RFP50N06, RF1S50N06SM
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
I
D
, DRAIN CURRENT (A)
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
T
C
, CASE TEMPERATURE (
o
C)
150
175
Unless Otherwise Specified
60
50
40
30
20
10
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
THERMAL IMPEDANCE
0.5
0.2
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
-5
10
10
-4
10
-3
10
-2
10
-1
t
1
, RECTANGULAR PULSE DURATION (s)
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
0
10
1
t
1
P
DM
Z
θJC
, NORMALIZED
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
400
T
J
= MAX RATED
SINGLE PULSE
T
C
= 25
o
C
I
DM
, PEAK CURRENT (A)
10
3
FOR TEMPERATURES ABOVE 25
o
C
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
V
GS
= 20V
175
–
T C
I = I 25
-----------------------
-
150
I
D
, DRAIN CURRENT (A)
100
100µs
1ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
V
DSS(MAX)
= 60V
1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10ms
100ms
DC
100
V
GS
= 10V
10
2
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
40
10
-3
10
-2
10
-1
10
0
10
1
10
2
t, PULSE WIDTH (ms)
10
3
10
4
T
C
= 25
o
C
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2002 Fairchild Semiconductor Corporation
RFG50N06, RFP50N06, RF1S50N06SM Rev. B
RFG50N06, RFP50N06, RF1S50N06SM
Typical Performance Curves
300
I
AS,
AVALANCHE CURRENT (A)
Unless Otherwise Specified
(Continued)
125
V
GS
= 10V
STARTING T
J
= 25
o
C
I
D
, DRAIN CURRENT (A)
100
100
V
GS
= 8V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
V
GS
= 7V
75
10
STARTING T
J
= 150
o
C
If R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
50
V
GS
= 6V
V
GS
= 5V
V
GS
= 4V
25
1
0.01
If R
≠
0
t
AV
= (L/R) ln [(I
AS
*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
0.1
1
10
0
0
1.5
3.0
4.5
6.0
7.5
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
t
AV,
TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes 9321 and 9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
125
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
I
D
, DRAIN CURRENT (A)
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
-55
o
C
25
o
C
2.5
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
GS
= 10V, I
D
= 50A
175
o
C
75
1.5
50
1.0
25
0.5
0
0
1
2
3
4
5
6
7
8
9
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
0
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2.0
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
V
GS
= V
DS
, I
D
= 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
1.5
2.0
I
D
= 250µA
1.5
1.0
1.0
0.5
0.5
0
-80
-40
0
40
80
120
160
200
0
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
RFG50N06, RFP50N06, RF1S50N06SM Rev. B
RFG50N06, RFP50N06, RF1S50N06SM
Typical Performance Curves
4000
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
= C
DS
+ C
GD
C
ISS
2000
Unless Otherwise Specified
(Continued)
60
V
DD
= BV
DSS
45
V
DD
= BV
DSS
7.5
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
3000
30
0.75 BV
DSS
0.50 BV
DSS
15
0.75 BV
DSS
0.50 BV
DSS
5.0
1000
C
OSS
C
RSS
0.25 BV
DSS
0.25 BV
DSS
R
L
= 1.2Ω
I
g(REF)
= 1.45mA
V
GS
= 10V
20
I
g(REF)
I
g(ACT)
t, TIME (µs)
80
I
g(REF)
I
g(ACT)
2.5
0
0
5
10
15
20
25
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0
0
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
DUT
t
P
R
G
-
I
AS
V
DD
t
P
V
DS
V
DD
+
0V
I
AS
0.01Ω
0
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
t
ON
V
DS
V
DS
V
GS
R
L
+
t
OFF
t
d(OFF)
t
r
t
f
90%
t
d(ON)
90%
DUT
R
GS
V
GS
-
V
DD
0
10%
90%
10%
V
GS
0
10%
50%
PULSE WIDTH
50%
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. SWITCHING WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFG50N06, RFP50N06, RF1S50N06SM Rev. B
