Preliminary
Datasheet
RJK0629JPE
60 V - 85 A - Silicon N Channel MOS FET
High Speed Power Switching
Features
•
•
•
•
•
For Automotive application
AEC-Q101 compliant
Low on-resistance : R
DS(on)
= 3.75 mΩ typ.
Capable of 4.5 V gate drive
Low input capacitance : Ciss = 4100 pF typ
R07DS1075EJ0100
Rev.1.00
Jun 17, 2013
Outline
RENESAS Package code: PRSS0004AE-B
(Package name: LDPAK(S)-(1) )
4
2, 4
D
1
2
1G
3
1.
2.
3.
4.
Gate
Drain
Source
Drain
S
3
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body-drain diode reverse drain current
Body-drain diode reverse drain peak current
Avalanche current
Avalanche energy
Channel dissipation
Channel temperature
Storage temperature
Notes: 1.
2.
3.
4.
PW
≤
10
μs,
duty cycle
≤
1%
Tch = 25°C, Rg
≥
50
Ω
Tc = 25°C
AEC-Q101 compliant
Symbol
V
DSS
V
GSS
I
D
I
D
(pulse)
Note
1
I
DR
I
DR
(pulse)
Note
1
I
AP
Note
2
E
AR
Note
2
Pch
Note
3
Tch
Note
4
Tstg
Value
60
±20
85
340
85
340
55
259
120
175
–55 to +150
Unit
V
V
A
A
A
A
A
mJ
W
°C
°C
Thermal Impedance Characteristics
•
Channel to case thermal impedance
θch-c:
1.25°C/W
R07DS1075EJ0100 Rev.1.00
Jun 17, 2013
Page 1 of 6
RJK0629JPE
Preliminary
Electrical Characteristics
(Ta = 25°C)
Item
Gate to source leak current
Zero gate voltage drain current
Gate to source cutoff voltage
Static drain to source on state
resistance
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate to source charge
Gate to drain charge
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Body-drain diode forward voltage
Body-drain diode reverse recovery
time
Note:
5. Pulse test
Symbol
I
GSS
I
DSS
V
GS(off)
R
DS(on)
Ciss
Coss
Crss
Qg
Qgs
Qgd
t
d(on)
t
r
t
d(off)
t
f
V
DF
t
rr
Min
—
—
1.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
—
—
—
3.75
4.9
4100
1000
780
85
11
25
20
40
100
40
0.92
50
Max
±10
1
2.0
4.5
6.6
—
—
—
—
—
—
—
—
—
—
1.2
—
Unit
μA
μA
V
mΩ
mΩ
pF
pF
pF
nC
nC
nC
ns
ns
ns
ns
V
ns
Test Conditions
V
GS
=
±20
V, V
DS
= 0
V
DS
= 60 V, V
GS
= 0
I
D
= 1 mA, V
DS
= 10 V
I
D
= 43 A, V
GS
= 10 V
Note
5
I
D
= 43 A, V
GS
= 4.5 V
Note
5
V
DS
= 10 V, V
GS
= 0
f = 1 MHz
V
DD
= 25 V, V
GS
= 10 V,
I
D
= 85 A
I
D
= 43A, R
L
= 0.698
Ω,
V
GS
= 10 V, R
G
= 4.7
Ω
I
F
= 85 A, V
GS
= 0
Note
5
I
F
= 85 A, V
GS
= 0,
di
F
/dt = 100 A/μs
R07DS1075EJ0100 Rev.1.00
Jun 17, 2013
Page 2 of 6
RJK0629JPE
Preliminary
Main Characteristics
Power vs. Temperature Derating
200
1000
10
μ
s
Maximum Safe Operation Area
Pch (W)
150
Drain Current I
D
(A)
100
1
10
0
μ
s
s
m
Channel Dissipation
10
Operation
in this area
is limited R
DS(on)
PW
100
=
DC
s
m
io n
10
at
er
Op
1
50
0.1
0.01
0.1
Tc = 25°C
1 shot Pulse
0
50
100
150
200
1
10
100
Case Temperature
Tc (°C)
Drain to Source Voltage
V
DS
(V)
Typical Output Characteristics
100
10 V
5V
100
3V
Typical Transfer Characteristics
Tc = 175°C
Drain Current I
D
(A)
Drain Current I
D
(A)
80
10
25°C
−40°C
60
V
GS
= 2.7 V
1
40
0.1
20
Tc = 25°C
Pulse Test
0
5
10
0.01
0.001
0
V
DS
= 10 V
Pulse Test
1
2
3
4
5
Drain to Source Voltage V
DS
(V)
Drain Source Saturation Voltage vs.
Gate to Source Voltage
20
I
D
= 43 A
Pulse Test
15
Gate to Source Voltage V
GS
(V)
Static Drain to Source State Resistance
vs. Drain Current
100
Tc = 25°C
Pulse Test
Static Drain to Source On State Resistance
R
DS(on)
(mΩ)
10
Tc = 175°C
Static Drain to Source On State Resistance
R
DS(on)
(mΩ)
10
V
GS
= 4.5 V
10 V
5
25°C
−40°C
0
0
4
8
12
16
20
1
1
10
100
Gate to Source Voltage V
GS
(V)
Drain Current I
D
(A)
R07DS1075EJ0100 Rev.1.00
Jun 17, 2013
Page 3 of 6
RJK0629JPE
Static Drain to Source on State Resistance
vs. Temperature
20
Pulse Test
I
D
= 43 A
10000
Preliminary
Typical Capacitance vs.
Drain to Source Voltage
Static Drain to Source On State Resistance
R
DS(on)
(mΩ)
Capacitance C (pF)
16
Ciss
3000
12
V
GS
= 4.5 V
8
1000
Coss
Crss
Tc = 25°C
V
GS
= 0
f = 1 MHz
0
5
10
15
20
25
30
4
10 V
300
0
−50
100
0
50
100
150
200
Case Temperature Tc (°C)
Drain to Source Voltage V
DS
(V)
Reverse Drain Current vs.
Source to Drain Voltage
Gate to Source Voltage V
GS
(V)
20
100
Dynamic Input Characteristics
Drain to Source Voltage V
DS
(V)
50
V
GS
16
Reverse Drain Current I
DR
(A)
Tc = 25°C
I
D
= 85 A
V
DD
= 25 V
10 V
5V
V
DS
10 V
80
Tc = 25°C
Pulse Test
40
30
12
60
20
V
DD
= 25 V
10 V
5V
40
80
120
160
8
40
V
GS
= 0,
−5
V
10
4
0
200
20
0
0
0.4
0.8
1.2
1.6
2.0
Gate Charge Qg (nC)
Source to Drain Voltage V
SD
(V)
Avalanche Energy vs.
Channel Temperature Derating
Repetitive Avalanche Energy E
AR
(mJ)
500
I
AP
= 55 A
V
DD
= 25 V
duty < 0.1 %
Rg
≥
50
Ω
400
300
200
100
0
25
50
75
100
125
150
175
Channel Temperature Tch (°C)
R07DS1075EJ0100 Rev.1.00
Jun 17, 2013
Page 4 of 6
RJK0629JPE
Normalized Transient Thermal Impedance
γ
s (t)
Normalized Transient Thermal Impedance vs. Pulse Width
10
Preliminary
1
D=1
0.5
0.2
0.1
0.1
0.05
θch
– c(t) =
γs
(t) •
θch
– c
θch
– c = 1.25°C/W, Tc = 25°C
0.01
u
tp
lse
P
DM
PW
T
D=
0.02
1s
ho
PW
T
0.01
10
μ
100
μ
1m
10 m
100 m
1
10
Pulse Width PW (s)
Avalanche Test Circuit
V
DS
Monitor
L
I
AP
Monitor
E
AR
=
Avalanche Waveform
1
2
L
•
I
AP
•
2
V
DSS
V
DSS
– V
DD
V
(BR)DSS
Rg
D. U. T
V
DD
I
AP
V
DS
Vin
15 V
50
Ω
I
D
0
V
DD
Switching Time Test Circuit
Vin Monitor
D.U.T.
Rg
R
L
V
DS
= 30 V
Vin
Vout
Vin
10 V
Vout
Monitor
Switching Time Waveform
90%
10%
10%
10%
90%
td(on)
tr
90%
td(off)
tf
R07DS1075EJ0100 Rev.1.00
Jun 17, 2013
Page 5 of 6
FPGA/CPLD
