S29PL-J
128-/128-/64-/32-Mbit (8/8/4/2M x 16-Bit)
3V, Flash with Enhanced VersatileIO™
Distinctive Characteristics
Architectural Advantages
128-/128-/64-/32-Mbit Page Mode devices
– Page size of 8 words: Fast page read access from random
locations within the page
Single power supply operation
– Full Voltage range: 2.7 to 3.6 V read, erase, and program
operations for battery-powered applications
Dual Chip Enable inputs (only in PL129J)
– Two CE# inputs control selection of each half of the
memory space
Simultaneous Read/Write Operation
– Data can be continuously read from one bank while
executing erase/program functions in another bank
– Zero latency switching from write to read operations
FlexBank Architecture (PL127J/PL064J/PL032J)
– 4 separate banks, with up to two simultaneous operations
per device
– Bank A:
PL127J -16 Mbit (4 Kw
8 and 32 Kw
31)
PL064J - 8 Mbit (4 Kw
8 and 32 Kw
15)
PL032J - 4 Mbit (4 Kw
8 and 32 Kw
7)
– Bank B:
PL127J - 48 Mbit (32 Kw
96)
PL064J - 24 Mbit (32 Kw
48)
PL032J - 12 Mbit (32 Kw
24)
– Bank C:
PL127J - 48 Mbit (32 Kw
96)
PL064J - 24 Mbit (32 Kw
48)
PL032J - 12 Mbit (32 Kw
24)
– Bank D:
PL127J -16 Mbit (4 Kw
8 and 32 Kw
31)
PL064J - 8 Mbit (4 Kw
8 and 32 Kw
15)
PL032J - 4 Mbit (4 Kw
8 and 32 Kw
7)
FlexBank Architecture (PL129J)
– 4 separate banks, with up to two simultaneous operations
per device
– CE#1 controlled banks:
Bank 1A: PL129J - 16-Mbit (4Kw
8 and 32Kw
31)
Bank 1B: PL129J - 48-Mbit (32Kw
96)
– CE#2 controlled banks:
Bank 2A: PL129J - 48-Mbit (32 Kw
96)
Bank 2B: PL129J - 16-Mbit (4 Kw
8 and 32 Kw
31)
Enhanced VersatileI/O (V
IO
) Control
– Output voltage generated and input voltages tolerated on
all control inputs and I/Os is determined by the voltage on
the V
IO
pin
– V
IO
options at 1.8 V and 3 V I/O for PL127J and PL129J
devices
– 3V V
IO
for PL064J and PL032J devices
Secured Silicon Sector region
– Up to 128 words accessible through a command sequence
– Up to 64 factory-locked words
– Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 110-nm process technology
Data Retention: 20 years typical
Cycling Endurance: 1 million cycles per sector typical
Performance Characteristics
High Performance
– Page access times as fast as 20 ns
– Random access times as fast as 55 ns
Power consumption (typical values at 10 MHz)
– 45 mA active read current
– 17 mA program/erase current
– 0.2
A
typical standby mode current
Software Features
Software command-set compatible with JEDEC 42.4
standard
– Backward compatible with Am29F, Am29LV, Am29DL, and
AM29PDL families and MBM29QM/RM, MBM29LV,
MBM29DL, MBM29PDL families
CFI (Common Flash Interface) compliant
– Provides device-specific information to the system,
allowing host software to easily reconfigure for different
Flash devices
Erase Suspend / Erase Resume
– Suspends an erase operation to allow read or program
operations in other sectors of same bank
Program Suspend / Program Resume
– Suspends a program operation to allow read operation
from sectors other than the one being programmed
Unlock Bypass Program command
Reduces overall programming time when issuing multiple
program command sequences
Cypress Semiconductor Corporation
Document Number: 002-00615 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 10, 2016
S29PL-J
Password Sector Protection
– A sophisticated sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector
using a user-defined 64-bit password
Package options
– Standard discrete pinouts
11
8 mm, 80-ball Fine-pitch BGA (PL127J) (VBG080)
8.15
6.15 mm, 48-ball Fine pitch BGA (PL064J/PL032J)
(VBK048)
– MCP-compatible pinout
8
11.6 mm, 64-ball Fine-pitch BGA (PL127J)
7
9 mm, 56-ball Fine-pitch BGA (PL064J and PL032J)
Compatible with MCP pinout, allowing easy integration of
RAM into existing designs
– 20
14 mm, 56-pin TSOP (PL127J) (TS056)
Hardware Features
Ready/Busy# pin (RY/BY#)
– Provides a hardware method of detecting program or
erase cycle completion
Hardware reset pin (RESET#)
– Hardware method to reset the device to reading array data
WP#/ ACC (Write Protect/Acceleration) input
– At V
IL
, hardware level protection for the first and last two
4K word sectors.
– At V
IH
, allows removal of sector protection
– At V
HH
, provides accelerated programming in a factory
setting
Persistent Sector Protection
– A command sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector
– Sectors can be locked and unlocked in-system at V
CC
level
Document Number: 002-00615 Rev. *B
Page 2 of 105
S29PL-J
Contents
1.
2.
2.1
2.2
3.
4.
5.
6.
7.
8.
8.1
8.2
8.3
8.4
8.5
8.6
9.
10.
11.
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
12.
12.1
12.2
12.3
12.4
13.
13.1
13.2
13.3
13.4
14.
14.1
14.2
14.3
14.4
14.5
General Description.....................................................
4
Simultaneous Read/Write
Operation with Zero Latency
...................................... 4
Page Mode Features ..................................................... 5
Standard Flash Memory Features ................................. 5
Ordering Information
................................................... 6
Product Selector Guide
............................................... 8
Block Diagram..............................................................
8
Simultaneous Read/Write Block Diagram..................
9
Simultaneous Read/Write
Block Diagram (PL129J)............................................
10
Connection Diagrams................................................
Special Package Handling Instructions........................
80-Ball Fine-Pitch BGA—PL127J ................................
64-Ball Fine-Pitch BGA—
MCP Compatible—PL127J ..........................................
48-Ball Fine-Pitch BGA,
PL064J and PL032J.....................................................
56-Pin TSOP 20 x 14 mm ............................................
56-Ball Fine-Pitch Ball Grid Array,
PL064J and PL032J.....................................................
11
11
11
12
13
14
15
14.6 Secured Silicon Sector Flash Memory Region ............. 55
14.7 Hardware Data Protection............................................. 57
15.
16.
16.1
16.2
16.3
16.4
Common Flash Memory Interface (CFI)
.................... 58
Command Definitions.................................................
61
Reading Array Data ...................................................... 61
Reset Command ........................................................... 61
Autoselect Command Sequence .................................. 62
Enter/Exit Secured Silicon Sector
Command Sequence .................................................... 62
16.5 Word Program Command Sequence............................ 63
16.6 Chip Erase Command Sequence ................................. 64
16.7 Sector Erase Command Sequence .............................. 65
16.8 Erase Suspend/Erase Resume Commands ................. 66
16.9 Program Suspend/Program Resume Commands ........ 67
16.10Command Definitions Tables ....................................... 67
17.
17.1
17.2
17.3
17.4
17.5
17.6
17.7
18.
19.
20.
21.
21.1
21.2
21.3
21.4
21.5
21.6
Write Operation Status
............................................... 71
DQ7: Data# Polling ....................................................... 71
RY/BY#: Ready/Busy#.................................................. 72
DQ6: Toggle Bit I .......................................................... 72
DQ2: Toggle Bit II ......................................................... 74
Reading Toggle Bits DQ6/DQ2..................................... 74
DQ5: Exceeded Timing Limits ...................................... 74
DQ3: Sector Erase Timer.............................................. 75
Absolute Maximum Ratings.......................................
76
Operating Ranges
....................................................... 77
DC Characteristics......................................................
78
AC Characteristic........................................................
79
Test Conditions ............................................................. 79
Switching Waveforms ................................................... 80
Read Operations........................................................... 80
Reset ............................................................................ 82
Erase/Program Operations ........................................... 83
Timing Diagrams........................................................... 84
Pin Description...........................................................
16
Logic Symbol
............................................................. 17
Device Bus Operations..............................................
Requirements for Reading Array Data.........................
Simultaneous Read/Write Operation ...........................
Writing Commands/Command Sequences..................
Standby Mode..............................................................
Automatic Sleep Mode.................................................
RESET#: Hardware Reset Pin.....................................
Output Disable Mode ...................................................
Autoselect Mode ..........................................................
Selecting a Sector Protection Mode.............................
Sector Protection
.......................................................
Persistent Sector Protection ........................................
Password Sector Protection.........................................
WP# Hardware Protection ...........................................
Selecting a Sector Protection Mode.............................
Persistent Sector Protection.....................................
Persistent Protection Bit (PPB) ....................................
Persistent Protection Bit Lock (PPB Lock)...................
Dynamic Protection Bit (DYB)......................................
Persistent Sector Protection Mode Locking Bit............
Password Protection Mode.......................................
Password and Password Mode Locking Bit.................
64-bit Password ...........................................................
Write Protect (WP#) .....................................................
High Voltage Sector Protection....................................
Temporary Sector Unprotect........................................
17
18
19
19
20
20
20
21
43
47
49
49
49
49
49
50
50
50
50
51
52
52
52
53
53
55
22. Protect/Unprotect........................................................
88
22.1 Controlled Erase Operations......................................... 90
23. Pin Capacitance
.......................................................... 93
23.1 BGA Pin Capacitance ................................................... 93
23.2 TSOP Pin Capacitance ................................................. 93
24. Physical Dimensions
.................................................. 94
24.1 VBG080—80-Ball Fine-pitch
Ball Grid Array 8 x 11 mm Package (PL127J) .............. 94
24.2 VBH064—64-Ball Fine-pitch
Ball Grid Array 8 x 11.6 mm package (PL127J)............ 95
24.3 VBK048—48-Ball Fine-pitch
Ball Grid Array 8.15 x 6.15 mm package
(PL032J and PL064J)...................................................... 96
24.4 VBU056—56-Ball Fine-pitch
BGA 7 x 9mm package (PL064J and PL032J) ............. 97
24.5 TS056—20 x 14 mm, 56-pin TSOP (PL127J)............... 98
25.
Revision Summary......................................................
99
Page 3 of 101
Document Number: 002-00615 Rev. *B
S29PL-J
1. General Description
The PL127J/PL129J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash
memory device organized as 8/8/4/2 Mwords. The devices are offered in the following packages:
– 11 mm
8 mm, 80-ball Fine-pitch BGA standalone (PL127J)
– 8 mm
11.6 mm, 64-ball Fine-pitch BGA multi-chip compatible (PL127J)
– 8.15 mm
6.15 mm, 48-ball Fine-pitch BGA standalone (PL064J/PL032J)
– 7 mm
9 mm, 56-ball Fine-pitch BGA multi-chip compatible (PL064J and PL032J)
– 20 mm
14 mm, 56-pin TSOP (PL127J)
The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers.
A 12.0 V V
PP
is not required for write or erase operations.
2. Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space into 4 banks, which
can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall
system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from
another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting
for the completion of a program or erase operation, greatly improving system performance.
The device can be organized in both top and bottom sector configurations. The banks are organized as follows:
Bank
A
B
C
D
Bank
1A
1B
2A
2B
PL127J Sectors
16 Mbit (4 Kw
8 and 32 Kw
31)
48 Mbit (32 Kw
96)
48 Mbit (32 Kw
96)
16 Mbit (4 Kw x 8 and 32 Kw
31)
PL064J Sectors
8 Mbit (4 Kw
8 and 32 Kw
15)
24 Mbit (32 Kw
48)
24 Mbit (32 Kw
48)
8 Mbit (4 Kw
8 and 32 Kw
15)
PL032J Sectors
4 Mbit (4 Kw
8 and 32 Kw
7)
12 Mbit (32 Kw
24)
12 Mbit (32 Kw
24)
4 Mbit (4 Kw
8 and 32 Kw
7)
CE# Control
CE1#
CE1#
CE2#
CE2#
PL129J Sectors
16 Mbit (4 Kw
8 and 32 Kw
31)
48 Mbit (32 Kw
96)
48 Mbit (32 Kw
96)
16 Mbit (4 Kw
8 and 32 Kw
31)
Document Number: 002-00615 Rev. *B
Page 4 of 101
S29PL-J
2.1
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of
random locations within that page.
2.2
Standard Flash Memory Features
The device requires a
single 3.0 volt power supply
(2.7 V to 3.6 V) for both read and write functions. Internally generated and
regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard.
Commands are written
to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine
that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase
command sequence.
The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle)
status bits.
After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of
memory. This can be achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume
feature enables the user to put erase on hold for any period of time to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from
the Secured Silicon Sector area (One Time Program area) after an erase suspend, then the user must use the proper command
sequence to enter and exit this region.
The
Program Suspend/Program Resume
feature enables the user to hold the program operation to read data from any sector that
is not selected for programming. If a read is needed from the Secured Silicon Sector area, Persistent Protection area, Dynamic
Protection area, or the CFI area, after a program suspend, then the user must use the proper command sequence to enter and exit
this region.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters
the
automatic sleep mode.
The system can also place the device into the standby mode. Power consumption is greatly reduced in
both these modes. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.
Document Number: 002-00615 Rev. *B
Page 5 of 101
