SDC-14600/05
TWO CHANNEL 14- AND 16-BIT
TRACKING S/D CONVERTERS
FEATURES
DESCRIPTION
The SDC-14600/05 Series are small
low cost dual synchro- or resolver-to-
digital converters. The SDC-14600
Series is fixed at 14 bits, the SDC-
14605 at 16 bits. The two channels
are independent tracking types but
share digital output pins and a com-
mon reference.
The velocity output (VEL) from the
SDC-14600/05 Series, which can be
used to replace a tachometer, is a 4 V
signal referenced to ground with a lin-
earity of 1% of output voltage.
A BIT output is optional and is a logic
line that indicates LOS or excessive
converter error. Due to pin limitations
this option will exclude the velocity
output (contact factory).
SDC-14600/05 Series converters are
available with operating temperature
ranges of 0°C to +70°C and -55°C to
+125°C, and MIL-PRF-38534 pro-
cessing is available.
APPLICATIONS
With its low cost, small size, high
accuracy, and versatile performance,
the SDC-14600/05 Series converters
are ideal for use in modern high-per-
formance military and industrial posi-
tion control systems. Typical applica-
tions include radar antenna position-
ing, navigation and fire control sys-
tems, motor control, and robotics.
•
•
•
•
•
Fixed 14- or 16-Bit Resolution
Small Size 28 Pin DDIP Package
Two Independent Converters
Low Cost
Velocity Output Eliminates
Tachometer
•
Optional BIT Output
•
High Reliability Single Chip
Monolithic
•
-55°C to +125°C Operating
Temperature Range
•
MIL-PRF-38534 Processing
Available
C
I
+REF -REF (Common)
S1
S2
S3
S4
HYSTERESIS
INTEGRATOR
INPUT OPTION
CONTROL
TRANSFORMER
R
I
GAIN
DEMODULATOR
VEL
14/16 BIT
UP/DOWN
COUNTER
VCO & TIMING
DATA LATCH
8
EM DATA
EL
INH (Common)
FIGURE 1. SDC-14600/05 BLOCK DIAGRAM
(one channel)
©
1991, 1999 Data Device Corporation
TABLE 1. SDC-14600/05 SPECIFICATIONS (Each Channel)
These specs apply over the rated power supply temperature and ref-
erence frequency ranges; 10% signal amplitude variation and 10%
harmonic distortion.
Each Channel unless stated otherwise
PARAMETER
RESOLUTION
ACCURACY
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT
Type
Voltage Range
Frequency
Input Impedance
single ended
differential
Common Mode Range
UNIT
Bits
Min
LSB
LSB
14
4(8) + 1 LSB
VALUE
16
2(4) + 1 LSB
TABLE 1. SDC-14600/05 SPECIFICATIONS (continued)
PARAMETER
DIGITAL INPUT/OUTPUT
Outputs
(continued)
Drive Capability
TTL
Each Channel
50 pF +
Logic 0; 1 TTL load
1.6 mA at 0.4 V max
Logic 1; 10 TTL loads
-0.4 mA at 2.8 V min
Logic 0; 100 mV max
driving
Logic 1; +5 V supply
minus 100 mV min
driving
UNIT
VALUE
1 max
1 max
(+REF -REF )
Common to Both Channels
differential
CMOS
2 & 11.8V units
90V unit
10-130
Vrms 2 - 35
See Note.
Hz 360 - 5000
Ohm 60k
Ohm 120k
Vpeak 50,
100 transient
270k min
540k min
200,
300 transient
SIGNAL INPUT CHARACTERISTICS
90V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
11.8V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
11.8V Resolver Input (L-L)
Zin single ended
Zin differential
Common Mode Voltage
2V Direct Input (L-L)
Voltage Range
Max Voltage No Damage
Input Impedance
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
Ohm
Ohm
V
Ohm
Ohm
V
Ohm
Ohm
V
Vrms
V
Ohm
Each Channel
123k
80k
180 max
52k
34k
30 max
70k
140k
30 max
2 nom 2.3 max
25 cont 100 pk transient
20 M // 10 pF min
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading =10 µA max P.U.
current source to +5 V // 5 pF
maximum
CMOS transient protected
DYNAMIC CHARACTERISTICS
Each Channel
Input Frequency
Bandwidth (Closed Loop)
Ka
A1
A2
A
B
Resolution
Tracking Rate
typical
minimum
Acceleration (1 LSB lag)
Settling Time (179° step max)
VELOCITY
CHARACTERISTICS
Polarity
Voltage Range (Full Scale)
Scale Factor
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
Noise
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
TEMPERATURE RANGE
Operating
-30X
-10X
Storage
PHYSICAL
CHARACTERISTICS
Size
Weight
Hz
Hz
1/s
2
1/s
1/s
1/s
1/s
bits
rps
rps
deg/s
2
msec
Device Type
60 Hz
400 Hz
47 - 5k
360-5k
15
103
830
53k
0.17
1.33
5k
40k
29
230
14.5
115
14
16
14
16
1.25 0.31
10
1
0.25
8
18
4.5 1160
1100 2500 140
Each Channel
Positive for increasing angle
4.5 typ, 4 min
10 typ
20 max
100 typ
200 max
1 typ
2 max
0.5 typ
1 max
5 typ
10max
15 typ
30 max
20 max
1 typ
2 max
Total Device
+5
-5
5
10
+7
-7
24 typ, 34 max
2.5
2
290
320
±V
±%
ppm/°C
±%
±%
mV
µV/°C
kOhm
(Vp/V)%
V
±%
V
mA
Inhibit (INH)(common)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 14(16)(EL)
Each Channel
Logic 0 inhibits ; Data
stable within 0.5 µs
Logic 0 enables; Data stable
within 150 ns
Logic 1 = High Impedance
Data High Z within 100 ns
Common to Both Channels
8 parallel lines; 2 bytes natural
binary angle, positive logic
°C
°C
°C
0 to +70
-55 to +125
-65 to +150
Output
Parallel Data [1-14(16)]
bits
in
(mm)
oz
1.48 x 0.78 x 0.2
(37.6 x 19.8 x 5.1)
0.66
Note: 47-5k for 90 V, 60 Hz; 360-5k for 90 V, 400 Hz
2
THEORY OF OPERATION
The SDC-14600/05 Series of converters are based upon a sin-
gle chip CMOS custom monolithic. They are implemented using
the latest IC technology which merges precision analog circuitry
with digital logic to form a complete high performance tracking
resolver to digital converter.
FIGURE 1 is the Functional Block Diagram of SDC-14600/05
Series. The converter operates with +5 Vdc power supplies.
Analog signals are referenced to analog ground, which is at
ground potential. The converter is made up of three main sec-
tions; an input front-end, a converter, and a digital interface. The
converter front-end differs for synchro, resolver and direct inputs.
An electronic Scott-T is used for synchro inputs, a resolver con-
ditioner for resolver inputs and a sine and cosine voltage follow-
er for direct inputs. These amplifiers feed the high accuracy
Control Transformer (CT). Its other input is the 14 bit digital
angle
φ.
Its output is an analog error angle, or difference angle,
between the two inputs. The CT performs the ratiometric trigono-
metric computation of SINθCOSφ - COSθSINφ = SIN(θ-φ) using
amplifiers, switches, logic and capacitors in precision ratios.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. In these converters ratioed capacitors
are used in the CT, instead of the more conventional precision
ratioed resistors. Capacitors used as computing elements with
op-amps need to be sampled to eliminate voltage drifting.
Therefore, the circuits are sampled at a high rate to eliminate this
drifting and at the same time to cancel out the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The dc error is inte-
grated yielding a velocity voltage which in turn drives a voltage
controlled oscillator (VCO). This VCO is an incremental integra-
tor (constant voltage input to position rate output) which togeth-
er with the velocity integrator forms a type II servo feedback
loop. A lead in the frequency response is introduced to stabilize
the loop and another lag at higher frequency is introduced to
reduce the gain and ripple at the carrier frequency and above.
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
- Error Gradient = 0.011 volts per LSB (CT+Error Amp+Demod)
- Integrator gain =
- VCO Gain =
1 volts per second per volt
RiCi
1
LSBs per second per volt
1.25RvCv
GENERAL SETUP CONSIDERATIONS
The following recommendations should be considered when
connecting the SDC-14600/05 Series converters:
1) Power supplies are ±5 Vdc. For lowest noise performance it is
recommended that a 0.1 µF or larger cap be connected from
each supply to ground near the converter package.
2) Direct inputs are referenced to A GND.
INHIBIT AND ENABLE TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 3,
angular output data is valid 500 nanoseconds maximum after the
application of the low-going inhibit pulse.
Output angle data is enabled onto the tri-state data bus in four
bytes. The Enable MSB (EM A or EM B) is used for the most sig-
nificant 8 bits and Enable LSB (EL A or EL B) is used for the
least significant bits. As shown in FIGURE 4, output data is valid
150 nanoseconds maximum after the application of a low-going
enable pulse. The tri-state data bus returns to the high imped-
ance state 100 nanoseconds maximum after the rising edge of
the enable signal.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined
from its functional block diagram and its bode plots (open and
closed loop); These are shown in FIGURES 1 and 2.
The open loop transfer function is as follows:
-1
2d
GAIN = 4
OPEN LOOP
oc
b/
t
(CRITICALLY DAMPED)
2A
ω
(rad/sec)
10B
- GAIN = 0.4
f
3db
= BW =
2 A (Hz)
π
Open Loop Transfer Function =
( )
S
(
S +1
10B
)
A
2
2
S +1
B
B
A
(B=A/2)
-6
db
/oc
t
where A is the gain coefficient
and B is the frequency of lead compensation
CLOSED LOOP
2A
2 2A
ω
(rad/sec)
FIGURE 2. BODE PLOTS
3
Dimensions in inches (mm).
INHIBIT
0.78 (MAX)
(19.81)
PIN NUMBERS ARE
FOR REF. ONLY
0.250 ±0.010 (TYP)
(6.35 ±0.25)
15
0.200 (MAX)
(5.08)
DATA
;;;;;;
500 ns MAX
DATA
VALID
0.600
(15.24)
14
FIGURE 3. INHIBIT TIMING
1.48 (MAX)
(37.59)
1.300
(33.02)
ENABLE
DATA
HIGH Z
FIGURE 4. ENABLE TIMING
; ;
150 ns MAX
DATA
VALID
1
PIN 1 DENOTED BY
CONTRASTING
COLORED BEAD
28
0.100 (TYP)
(2.54)
0.018±0.002 DIA (TYP)
(0.46 ±0.05)
100 ns MAX
HIGH Z
BOTTOM
VIEW
SIDE
VIEW
FIGURE 5. SDC-14600/05 MECHANICAL OUTLINE
NO FALSE 180° HANGUP
This feature eliminates the “false 180° reading” during instanta-
neous 180° step changes; this condition most often occurs when
the input is “electronically switched” from a digital-to-synchro
converter. If the “MSB” (or 180° bit) is “toggled” on and off, a con-
verter without the “false 180° hangup” feature may fail to
respond.
The condition is artificial, as a “real” synchro or resolver can not
change its output 180° instantaneously. The condition is most
often noticed during wraparound verification tests, simulations,
or troubleshooting.
1
2
3
4
5
6
7
8
9
S1A(S)
S2A(S)
S3A(S)
N.C.
TABLE 2. PINOUT (28 PIN)*
S1A(R) A GND(D) 28 +REF
S2A(R) +COS(D)
S3A(R) +SIN(D)
S4A(R) N.C.
/Bit 9
/Bit 10
/Bit 11
/Bit 12
/Bit 13
/Bit 14
/Bit 15**
/Bit 16**
(Inhibit)
(Velocity Output)
27 -REF
26 -5 V
25 VEL A
24 EM A
23 EL A
22 GND
21 +5 V
20 EL B
19 EM B
18 N.C.
17 S3B(S)
16 S2B(S)
15 S1B(S)
(+Reference Input)
(-Reference Input)
(Power Supply)
(Velocity Output)
(Enable MSBs)
(Enable LSBs)
(Ground)
(Power Supply)
(Enable LSBs)
(Enable MSBs)
S4B(R) N.C.
S3B(R) +SIN(D)
S2B(R) -COS(D)
S1B(R) A GND(D)
Bit 1(MSB)
Bit 2
Bit 3
Bit 4
Bit 5
10 Bit 6
11 Bit 7
12 Bit 8
13 INH
14 VEL B
* Note: (S) = Synchro; (R) = Resolver; (D) = 2 V Resolver Direct
** Note: SDC-14605 Series only
4
ORDERING INFORMATION
SDC-1460XT-X X X X
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
Blank = None of the Above
Accuracy:
2 = ±4 + 1 LSB
4 = ±2 minutes + 1 LSB (Not available with 14-bit units.)
Process Requirements:
0 = Standard DDC Processing, no Burn-In (See table below.)
1 = MIL-PRF-38534 Compliant
2
2 = B
1
3 = MIL-PRF-38534 Compliant with PIND Testing
2
4 = MIL-PRF-38534 Compliant with Solder Dip
2
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
2
6 = B
1
with PIND Testing
7 = B
1
with Solder Dip
8 = B
1
with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (See table.)
Temperature Grade/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
6 = Custom Part (reserved)
7 = Custom Part (reserved)
8 = 0°C to +70°C with Variables Test Data
Output Option:
Blank = Standard Velocity Output (VEL)
T = Built-In-Test Output, instead of VEL
Input Option:
0 = 11.8 V,
Synchro,
14 bit,
400 Hz
1 = 11.8 V,
Resolver,
14 bit,
400 Hz
2 = 90 V,
Synchro,
14 bit,
400 Hz
3 = 2 V,
Direct,
14 bit,
400 Hz
4 = 90 V,
Synchro,
14 bit,
60 Hz
5 = 11.8 V,
Synchro,
16 bit,
400 Hz
6 = 11.8 V,
Resolver,
16 bit,
400 Hz
7 = 90 V,
Synchro,
16 bit,
400 Hz
8 = 2 V,
Direct
16 bit,
400 Hz
9 = 90 V,
Synchro,
16 bit,
60 Hz
These products contain tin-lead solder finish as applicable to solder dip requirements.
For 400 Hz and 60 Hz reference frequencies use the SDC-14560 Series converters.
Drawings to DESC format available from factory
Notes:
1. Standard DDC Processing with burn-in and full temperature test—see table.
2. MIL-PRF-38534 product grading is designated with the following dash numbers:
Class H is a -11X, 13X, 14X, 15X, 41X, 43X, 44X, 45X
Class G is a -21X, 23X, 24X, 25X, 51X, 53X, 54X, 55X
Class D is a -31X, 33X, 34X, 35X, 81X, 83X, 84X, 85X
5
嵌入式系统
