designed for use in fast 12-bit data acquisition systems
and signal processing systems.
The SHC804 acquires a 10V signal change in less than
350ns to
±1/2LSB
at 12 bits. Throughput nonlinearity
error is guaranteed to be within
±1/2LSB
for 12-bit
systems. Stability over temperature is excellent, with
only
±5ppm/°C
of gain drift and
±4ppm
of FSR/°C of
charge offset drift over the –25 to +85°C temperature
range.
The
±25ps
maximum aperture uncertainty of the
SHC804 permits sampling (to
±0.01%
of Full Scale
Range) of signals with rates of change of up to 100V/µs.
This component is capable of accurately digitizing fast
changing signals at sample rates as high as 500k
samples per second.
The digital inputs (HOLD and HOLD) are TTL-
compatible. Power supply requirements are
±15V
and
+5V and the specification temperature range is –25°C
to +85°C. The SHC804 is packaged in a 24-pin dual-
in-line hermetic metal package. SHC804 is pin-com-
patible with other sample/holds on the market with
similar performance characteristics.
Sample/Hold
Analog Input
1000Ω
1000Ω
C
H
Sample/
Hold
Output
Switch
Drive
Hold
Analog
Common
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
At +25°C, rated power supplies and a 1kΩ output load, unless otherwise specified.
SHC804BM
PARAMETER
MIN
TYP
MAX
MIN
SHC804CM
TYP
MAX
UNITS
SAMPLE/HOLD INPUTS (without Input Buffer)
ANALOG
Voltage Range
R
IN
DIGITAL (HOLD, HOLD)
V
IH
V
IL
I
IH
, V
IN
= +2.7V
I
IL
, V
IN
= +0.4V
±10.25
±11
1.00
T
T
T
V
kΩ
V
V
µA
mA
+2.0
+0.8
+60
–1.2
T
T
T
T
SAMPLE/HOLD TRANSFER CHARACTERISTICS (without Input Buffer)
ACCURACY
Sample Mode
Gain
Gain Error
Temperature Coefficient
Linearity Error
Zero Offset
Temperature Coefficient
Hold Mode
Charge Offset
Temperature Coefficient
Droop Rate: at +25°C
+85°C
Throughput Nonlinearity
Power Supply Sensitivity
(2)
:
±V
CC
V
DD
DYNAMIC CHARACTERISTICS
Acquisition Time (with 10V Step)
to within:
±0.1%
(±10mV)
±0.01%
(±1mV)
Sample-to-Hold Settling Time
to within
±0.01%
(±1mV)
Sample-to-Hold Transient Amplitude
Aperture Delay TIme
(3)
Aperture Uncertainty
Sample Mode: Output Slew Rate
Full Power Bandwidth
Small Signal Bandwidth
Hold Mode Feedthrough Rejection
(10V Square Wave Input)
SAMPLE/HOLD OUTPUT
Voltage Range
Output Current
Short Circuit Protection
Output Impedance (at DC)
POWER SUPPLY REQUIREMENTS
Rated Voltage:
±V
CC
V
DD
Quiescent Current (No Load)
SHC804: +V
CC
–V
CC
V
DD
SHC803: +V
CC
–V
CC
V
DD
Power Dissipation: SHC804
TEMPERATURE RANGE
Specification
Storage
T
Specification same as SHC804BM.
NOTES: (1) FSR means Full Scale Range and is 20V for SHC804. (2) Sensitivity of offset plus charge offset. (3) With respect to HOLD. For HOLD add 5ns typical.
(4) With buffer connected to the sample/hold amplifier.
COMMON .............................................................. 0 to +18V
–V
CC
to V
CC
COMMON .............................................................. 0 to –18V
Voltage on Digital Inputs (pins 11 and 12) ........................... –0.5V to +7V
Power Dissipation ....................................................................... 1500mW
V
DD
to DCOM ................................................................................... –0.5V
Analog Output ............................................... Indefinite Short to V
CC
COM
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE INFORMATION
PRODUCT
SHC804BM
SHC804CM
PACKAGE
24-Pin
24-Pin
PACKAGE DRAWING
NUMBER
(1)
037
037
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
CONNECTION DIAGRAMS
SHC804CM, BM
V
OUT
1
2
3
4
5
6
7
Digital
Power
Supply
COM
8
+5V
9
10
11
12
V
DD
DCOM
Hold
Hold
NC 16
COM 15
NC 14
S/H In 13
Signal
Source
Analog
Output
NC
NC
NC
NC
NC
NC
NC
+V
CC
24
V
CC
COM 23
–V
CC
22
COM 21
NC 20
NC 19
NC 18
NC 17
1µF
+15V
1µF
COM
–15V
Analog
Power
Supply
PIN ASSIGNMENTS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NAME
Sample/Hold Output
NC
NC
NC
NC
NC
NC
NC
V
DD
DCOM
HOLD
HOLD
S/H In
NC
COM
NC
NC
NC
NC
NC
COM
–V
CC
V
CC
COM
+V
CC
DESCRIPTION
Analog voltage output
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Logic supply
Logic supply common
Logic “1” = HOLD
Logic “0” = HOLD
SHC804 input
Not connected
Signal common
Not connected
Not connected
Not connected
Not connected
Not connected
Signal common
–15V supply
Analog to power common, connected
to case
+15V supply
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
SHC804
DISCUSSION OF
SPECIFICATIONS
Throughput Nonlinearity is defined as total Hold mode,
nonadjustable, input to output error caused by charge offset,
gain nonlinearity, droop, feedthrough, and thermal tran-
sients. It is the inaccuracy due to these errors which cannot
be corrected by Offset and Gain adjustments.
Gain Error is the difference between the input and output
voltage magnitude (in the Sample mode) due to the amplifier
gain errors.
Droop Rate is the voltage decay at the output when in the
Hold mode due to storage capacitor and FET switch leakage
current and the input bias current of the output amplifier.
Feedthrough is the amount of output voltage change caused
by an input voltage change when the sample/hold is in the
Hold mode.
Aperture Delay Time is the time required to switch from
Sample to Hold. The time is measured from the 50% point
of the Hold mode control transition to the time at which the
output stops tracking the input.
Aperture Uncertainty Time is the nonrepeatability of aper-
ture delay time.
Acquisition Time is the time required for the sample/hold
output to settle to within a given error band of its final value
when the sample/hold is switched from Hold to Sample.
Charge Offset (Pedestal) is the output voltage change that
results from charge coupled into the Hold capacitor through
the gate capacitance of the switching field effect transistor.
This charge appears as an offset at the output.
Sample-to-Hold Switching Transient is the switching tran-
sient which appears on the output when the sample/hold is
switched from Sample to Hold. Both the magnitude and the
settling time of the transient are specified.
V
V
IN
Sample-to-Hold
Transient
V
OUT
Acquisition
Time
Droop
Sample
Hold
t
FIGURE 1. Definition of Acquisition Time, Droop and
Sample-to-Hold Transient.
INSTALLATION
GROUNDING AND BYPASSING
SHC804 has four COMMON pins (pins 10, 15, 21 and 23)
and all must be tied together and connected to the system
analog common (V
CC
COM) as close to the package as
possible. It is preferable to have a large ground plane
surrounding the sample/hold and have all four common pins
soldered directly to it. Note that the metal case is internally
connected to pin 23; therefore, care must be taken to avoid
a ground loop if the case is allowed to contact the ground
plane.
Most digital return currents pass through pin 10. Noise from
the switch-drive circuit may couple directly into the main op
amp summing junction, a very noise-sensitive node. Care
must be taken to insure that no voltage differences occur
between pin 10 and the other common pins. This is the
reason pin 10 must be connected directly to the ground
plane.
For the same reason, the logic supply should be kept as free
of noise as possible.
±V
CC
supply lines (pins 24 and 22) are
internally bypassed to common with 0.01µF capacitors. It is
recommended that the user install additional external 0.1µF
to 1µF tantalum bypass capacitors at each supply pin.
SAMPLE/HOLD CONTROL
A TTL logic “0” at pin 11 (or a logic “1” at pin 12) switches
the SHC804 into the Sample (track) mode. In this mode, the
device acts as a unity-gain inverting amplifier, the output
following the inverse of the input. A logic “1” at pin 11 (or
a logic “0” at pin 12) will switch the SHC804 into the Hold
mode. The output voltages will be held constant at the value
present when the Hold command is given.
If pin 11 is used, pin 12 must be connected to the DCOM
(pin 10). If pin 12 is used, pin 11 must be tied to V
DD
. Using
the HOLD and HOLD inputs as logic function may ad-
versely affect the charge offset (pedestal). A clean digital
signal (no overshoot) at the HOLD of HOLD inputs will
also reduce charge offset errors. Pins 11 and 12 present less
than one standard TTL load (two LSTTL loads) to the digital
drive circuit.
OPERATION
In the Sample (track) mode the circuit acts as a unity-gain
inverting amplifier. In the Hold mode, the capacitor, C
H
,
holds the value of the output at the time the unit was
switched to the Hold mode. Additional circuits compensate
for switching transients and provide switch leakage current
cancellation. The amplifier provides high current drive and
low output impedance to external loads.
GAIN, OFFSET, CHARGE OFFSET
SHC804 has been internally-trimmed to eliminate the need
for external trim potentiometers for Gain, Offset (in Sample
mode) and Charge Offset (Pedestal). System Gain and Off-
set errors can be adjusted elsewhere in the system, at an
input amplifier preceding the sample/hold, or at an analog-
to-digital converter following the sample/hold.
®
SHC804
4
OUTPUT LOADING
Care must be taken when loading the output of the SHC804
to avoid possible oscillations, current limiting and perfor-
mance variations over temperature.
The maximum capacitive load to avoid oscillations is about
300pF. Recommended resistive load is 500Ω or more, al-
though values as low as 250Ω may be used. Acquisition and
sample-to-hold settling times are relatively unaffected by
resistive loads down to 250Ω in parallel with capacitive
loads up to 100pF. Higher capacitances will affect acquisi-
tion and settling times.
ANALOG SIGNAL SOURCE CONSIDERATIONS
The output impedance of the signal source driving the
SHC804 will affect the accuracy of the sample and hold
operation both statically (at DC) and dynamically. The
output impedance of the signal source should be low and
remain low over a wide bandwidth. A small capacitor at the
driving source may help to improve the charge offset errors
