Si5341/40 Rev D Data Sheet
Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock
Generator
The any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL
with proprietary MultiSynth
™
fractional synthesizer technology to offer a versatile and
high performance clock generator platform. This highly flexible architecture is capable
of synthesizing a wide range of integer and non-integer related frequencies up to 1
GHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter per-
formance with 0 ppm error. Each of the clock outputs can be assigned its own format
and output voltage enabling the Si5341/40 to replace multiple clock ICs and oscillators
with a single device making it a true "clock tree on a chip."
The Si5341/40 can be quickly and easily configured using ClockBuilderPro software.
Custom part numbers are automatically assigned using a
ClockBuilder Pro
™
for fast,
free, and easy factory pre-programming or the Si5341/40 can be programmed via I2C
and SPI serial interfaces.
KEY FEATURES
• Generates any combination of output
frequencies from any input frequency
• Ultra-low jitter of 90 fs rms
• Input frequency range:
• External crystal: 25 to 54 MHz
• Differential clock: 10 to 750 MHz
• LVCMOS clock: 10 to 250 MHz
• Output frequency range:
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
• Highly configurable outputs compatible with
LVDS, LVPECL, LVCMOS, CML, and HCSL
with programmable signal amplitude
• Si5341: 4 input, 10 output, 64-QFN 9x9 mm
• Si5340: 4 input, 4 output, 44-QFN 7x7 mm
Applications:
• Clock tree generation replacing XOs, buffers, signal format translators
• Any-frequency clock translation
• Clocking for FPGAs, processors, memory
• Ethernet switches/routers
• OTN framers/mappers/processors
• Test equipment and instrumentation
• Broadcast video
25-54 MHz XTAL
XA
4 Input
Clocks
IN0
IN1
IN2
OSC
÷INT
÷INT
÷INT
PLL
XB
MultiSynth
MultiSynth
MultiSynth
MultiSynth
MultiSynth
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
Zero Delay
OUT0
OUT1
Si5340
Up to 10
Output Clocks
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Si5341
OUT8
OUT9
FB_IN
Status Flags
I2C / SPI
÷INT
Status Monitor
Control
NVM
÷INT
÷INT
÷INT
÷INT
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Rev. 1.0
Si5341/40 Rev D Data Sheet
Features List
1. Features List
The Si5341/40 Rev D features are listed below:
• Generates any combination of output frequencies from any in-
put frequency
• Ultra-low jitter of 90 fs rms
• Input frequency range:
• External crystal: 25 to 54 MHz
• Differential clock: 10 to 750 MHz
• LVCMOS clock: 10 to 250 MHz
• Output frequency range:
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with programmable signal ampli-
tude
• Locks to gapped clock inputs
• Optional zero delay mode
• Glitchless on the fly output frequency changes
• DCO mode: as low as 0.001 ppb steps
• Core voltage
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
• Independent output clock supply pins
• 3.3 V, 2.5 V, or 1.8 V
• Serial interface: I2C or SPI
• In-circuit programmable with non-volatile OTP memory
• ClockBuilder Pro software simplifies device configuration
• Si5341: 4 input, 10 output, 64-QFN 9x9 mm
• Si5340: 4 input, 4 output, 44-QFN 7x7 mm
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
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Si5341/40 Rev D Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Si5341/40 Ordering Guide
Number of In-
put/Output
Clocks
Ordering Part Number
(OPN)
Si5341
Si5341A-D-GM
1, 2
Si5341B-D-GM
1, 2
Si5341C-D-GM
1, 2
Si5341D-D-GM
1, 2
Si5340
Si5340A-D-GM
1, 2
Si5340B-D-GM
1, 2
Si5340C-D-GM
1, 2
Si5340D-D-GM
1, 2
Si5341/40-D-EVB
Si5341-D-EVB
Si5340-D-EVB
Note:
Output Clock Frequency
Range (MHz)
Frequency Syn-
thesis Mode
Package
Temperature
Range
0.0001 to 1028 MHz
4/10
0.0001 to 350 MHz
0.0001 to 1028 MHz
0.0001 to 350 MHz
Integer and
Fractional
Integer Only
64-QFN
9x9 mm
–40 to 85 °C
0.0001 to 1028 MHz
4/4
0.0001 to 350 MHz
0.0001 to 1028 MHz
0.0001 to 350 MHz
Integer and
Fractional
Integer Only
44-QFN
7x7 mm
–40 to 85 °C
—
—
—
Evaluation
Board
—
1. Add an R at the end of the OPN to denote tape and reel ordering options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by Silicon Labs and the ClockBuild-
er Pro software utility. Custom part number format is: e.g., Si5341A-Dxxxxx-GM, where "xxxxx" is a unique numerical sequence
representing the preprogrammed configuration.
3. See
3.9 Custom Factory Preprogrammed Devicesand 3.10 Enabling Features and/or Configuration Settings Not Available in
ClockBuilder Pro for Factory Pre-Programmed Devices
for important notes about specifying a preprogrammed device to use fea-
tures or device register settings not yet available in CBPro.
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Rev. 1.0 | 2
Si5341/40 Rev D Data Sheet
Ordering Guide
Si534fg-Rxxxxx-GM
Timing product family
f = Multi-PLL clock
family
member (7, 6)
g = Device
grade
(A, B, C, D)
Product
Revision*
Custom ordering part number (OPN) sequence ID**
Package, ambient temperature range (QFN, -40 °C to +85°C)
*See Ordering Guide table for current product revision
** 5 digits; assigned by ClockBuilder Pro
Figure 2.1. Ordering Part Number Fields
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Si5341/40 Rev D Data Sheet
Functional Description
3. Functional Description
The Si5340/41-D combines a wide band PLL with next generation MultiSynth technology to offer the industry's most versatile and high
performance clock generator. The PLL locks to either an external
crystal
between XA/XB or to an external
clock
connected to XA/XB
or IN0, 1, 2. A fractional or integer multiplier takes the selected input clock or cystal frequency up to a very high frequency that is then
divided by the MultiSynth output stage to any frequency in the range of 100 Hz to 1 GHz on each output. The MultiSynth stage can
divide by both integer and fractional values. The high-resolution fractional MultiSynth dividers enable true any-frequency input to any-
frequency on any of the outputs. The output drivers offer flexible output formats which are independently configurable on each of the
outputs. This clock generator is fully configurable via its serial interface (I
2
C/SPI) and includes in-circuit programmable non-volatile
memory.
3.1 Power-up and Initialization
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-
tion period is complete. No clocks will be generated until the initialization is done. There are two types of resets available. A hard reset
is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be restored to
their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A soft reset
bypasses the NVM download. It is simply used to initiate register configuration changes.
Power-Up
Hard Reset
bit asserted
RSTb
pin asserted
NVM download
Soft Reset
bit asserted
Initialization
Serial interface
ready
Figure 3.1. Si5341 Power-Up and Initialization
3.2 Frequency Configuration
The phase-locked loop is fully contained and does not require external loop filter components to operate. Its function is to phase lock to
the selected input and provide a common reference to the MultiSynth high-performance fractional dividers.
A crosspoint mux connects any of the MultiSynth divided frequencies to any of the outputs drivers. Additional output integer dividers
provide further frequency division by an even integer from 2 to (2^25)-2. The frequency configuration of the device is programmed by
setting the input dividers (P), the PLL feedback fractional divider (Mn/Md), the MultiSynth fractional dividers (Nn/Nd), and the output
integer dividers (R). Silicon Labs's ClockBuilder Pro configuration utility determines the optimum divider values for any desired input
and output frequency plan.
3.3 Inputs
The Si5340/41-D requires either an external crystal at its XA/XB pins or an external clock at XA/XB or IN0, 1, 2.
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Rev. 1.0 | 4
FPGA/CPLD
