S i 5 3 5 0 A- B
W
EB
-C
USTOMIZABLE
A
NY
- F
R E QUE N C Y
CMOS C
LOCK
G
ENERATOR
Features
www.silabs.com/custom-timing
Generates up to 8 non-integer-related
frequencies from 8 kHz to 160 MHz
Exact frequency synthesis at each
output (0 ppm error)
Glitchless frequency changes
Low output period jitter: < 70 ps pp, typ
Configurable Spread Spectrum
selectable at each output
User-configurable control pins:
Output Enable (OEB_0/1/2)
Power Down (PDN)
Frequency Select (FS_0/1)
Spread Spectrum Enable (SSEN)
Supports static phase offset
Rise/fall time control
Operates from a low-cost, fixed
frequency crystal: 25 or 27 MHz
Separate voltage supply pins:
Core VDD: 2.5 V or 3.3 V
Output VDDO: 1.8V, 2.5 V or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
(<40 mA)
Available in 2 packages types:
10-MSOP: 3 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compatible
Supports HCSL jitter compatible
swing
10-MSOP
20-QFN
Ordering Information:
See page 17
Applications
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Residential gateways
Networking/communication
Servers, storage
XO replacement
Description
Th
e Si5350A is a user-definable custom clock generator that is ideally suited for
replacing crystals and crystal oscillators in cost-sensitive applications. Based on a
PLL + high resolution fractional divider MultiSynth
TM
architecture, the Si5350A can
generate any frequency up to 160 MHz on each of its outputs with 0 ppm error.
Spread spectrum is selectable (on/off) on any of the outputs. Custom pin-controlled
Si5350A devices can be requested using the ClockBuilder web-based part number
utility
(www.silabs.com/ClockBuilder).
Functional Block Diagram
20-QFN
XA
PLLA
OSC
Multi
Synth
0
Multi
Synth
1
PLLB
Multi
Synth
2
Multi
Synth
3
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
10-MSOP
XB
XA
OSC
PLLA
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
CLK0
CLK1
CLK2
P0
P1
Control
Logic
XB
PLLB
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
Multi
Synth
7
P0
P1
Control
Logic
Si5350A
P2
P3
P4
Si5350A
Rev. 0.75 10/12
Copyright © 2012 by Silicon Laboratories
Si5350A-B
Si5350A-B
2
Rev. 0.75
Si5350A-B
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Si5350A Replaces Multiple Clocks and XOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Configuring the Si5350A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. Crystal Inputs (XA, XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. Output Clocks (CLK0–CLK7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3. Programmable Control Pins (P0–P4) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2. 10-pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2. 10-pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev. 0.75
3
Si5350A-B
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Core Supply Voltage
Symbol
T
A
V
DD
Test Condition
Min
–40
3.0
2.25
1.71
Output Buffer Voltage
V
DDOx
2.25
3.0
Typ
25
3.3
2.5
1.8
2.5
3.3
Max
85
3.60
2.75
1.89
2.75
3.60
Unit
°C
V
V
V
V
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD
and VDDOx can be operated at independent voltages. Power supply sequencing for VDD and VDDOx requires that all
VDDOx be powered up either before or at the same time as VDD.
Table 2. DC Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Core Supply Current*
Output Buffer Supply
Current (Per Output)*
Input Current
Symbol
I
DD
Test Condition
Enabled 3 outputs
Enabled 8 outputs
Power Down (PDN = VDD)
Min
—
—
—
—
—
—
—
Typ
20
25
—
2.2
—
—
50
Max
30
40
50
5.0
10
30
—
Unit
mA
mA
µA
mA
µA
µA
I
DDOx
I
P1-P4
I
P0
C
L
= 5 pF
Pins P1, P2, P3, P4
V
P1-P4
< 3.6 V
Pin P0
3.3 V VDDO, default high
drive.
Output Impedance
Z
OI
*Note:
Output clocks less than or equal to 100 MHz.
4
Rev. 0.75
Si5350A-B
Table 3. AC Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Powerup Time
Powerdown Time
Output Enable Time
Output Frequency Transition Time
Spread Spectrum Frequency
Deviation
Spread Spectrum Modulation Rate
Symbol
T
RDY
T
PD
T
OE
T
FREQ
SS
DEV
SS
MOD
Test Condition
From V
DD
= V
DDmin
to valid output
clock, C
L
= 5 pF, f
CLKn
> 1 MHz
From V
DD
= V
DDmin
, C
L
= 5 pF,
f
CLKn
> 1 MHz
From OEB assertion to valid clock
output, C
L
= 5 pF, f
CLKn
> 1 MHz
f
CLKn
> 1 MHz
Down spread
Min
—
—
—
—
–0.5
30
Typ
2
5
—
—
—
31.5
Max
10
100
10
10
–2.5
33
Unit
ms
ms
µs
µs
%
kHz
Table 4. Input Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Crystal Frequency
P0-P4 Input Low Voltage
P0-P4 Input High Voltage
Symbol
f
XTAL
V
IL_P0-4
V
IH_P0-4
Test Condition
Min
25
–0.1
0.7 x V
DD
Typ
—
—
—
Max
27
0.3 x V
DD
3.60
Unit
MHz
V
V
Table 5. Output Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Frequency Range
Load Capacitance
Duty Cycle
Rise/Fall Time
Output High Voltage
Output Low Voltage
Symbol
F
CLK
C
L
DC
t
r
/t
f
V
OH
V
OL
Test Condition
F
CLK
< 100 MHz
Measured at V
DD
/2
20%–80%, C
L
= 5 pF
Min
0.008
—
45
—
V
DD
– 0.6
—
Typ
—
—
50
1
—
—
40
70
Max
160
15
55
1.5
—
0.6
95
Unit
MHz
pF
%
ns
V
V
Period Jitter*
J
PER
20-QFN, 4 outputs running,
1 per VDDO
10-MSOP or 20-QFN,
all outputs running
—
—
ps pk-pk
140
*Note:
Measured over 10k cycles. Jitter is highly dependent on device frequency configuration. Specifications represent a
"worst case, real world" frequency plan; actual performance may be substantially better. For 3 output 10-MSOP
package, measured with clock outputs of 74.25, 24.576, 48 MHz. For 8 output 20-QFN package, measured with clock
outputs of 33.33, 74.25, 27, 24.576, 22.5792, 28.322, 125, 48 MHz.
Rev. 0.75
5
