SL74HC14
Hex Schmitt-Trigger Inverter
High-Performance Silicon-Gate CMOS
The SL74HC14 is identical in pinout to the LS/ALS14, LS/ALS04. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC14 is useful to “square up” slow input rise and fall times.
Due to the hysteresis voltage of the Schmitt trigger, the SL74HC14A
finds applications in noisy environments.
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC14N Plastic
SL74HC14D SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
A
L
H
PIN 14 =V
CC
PIN 7 = GND
Output
Y
H
L
SLS
System Logic
Semiconductor
SL74HC14
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
Min
2.0
0
-55
-
Max
6.0
V
CC
+125
No
Limit*
Unit
V
V
°C
ns
* When V
IN
≈50%
V
CC
, I
CC
> 1mA
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs mu st be left open.
SLS
System Logic
Semiconductor
SL74HC14
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
1.0
2.3
3.0
0.9
2.0
2.6
0.3
0.9
1.2
1.2
2.25
3.0
0.2
0.4
0.5
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
1.0
≤85
°C
1.5
3.15
4.2
0.95
2.25
2.95
0.95
2.05
2.65
0.3
0.9
1.2
1.2
2.25
3.0
0.2
0.4
0.5
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
10
≤125
°C
1.5
3.15
4.2
0.95
2.25
2.95
0.95
2.05
2.65
0.3
0.9
1.2
1.2
2.25
3.0
0.2
0.4
0.5
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
40
µA
µA
V
Unit
V
T
+max
Maximum Positive-
Going Input Threshold
Voltage
Minimum Positive-
Going Input Threshold
Voltage
Maximum Negative-
Going Input Threshold
Voltage
Minimum Negative-
Going Input Threshold
Voltage
Maximum Hysteresis
Voltage
Minimum Hysteresis
Voltage
Minimum High-Level
Output Voltage
V
OUT
=0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V
I
OUT
≤
20
µA
V
OUT
=V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
IN
≤V
T
-min
I
OUT
≤
20
µA
V
IN
≤V
T
-min
I
OUT
≤4mA
I
OUT
≤5.2mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.5
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
T
+min
V
V
T
-max
V
V
T
-min
V
V
H
max
Note 1
V
H
min
Note 1
V
OH
V
V
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
≥V
T
+max
I
OUT
≤
20
µA
V
IN
≥V
T
+max
I
OUT
≤
4mA
I
OUT
≤5.2mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
Note: 1 V
H
min>(V
T
+min)-(V
T
-max); V
H
max=(V
T
+max)-(V
T
-min)
.
SLS
System Logic
Semiconductor
SL74HC14
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, Input A to
Output Y (Figures 1 and 2)
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
Maximum Input Capacitance
V
2.0
4.5
6.0
2.0
4.5
6.0
-
Guaranteed Limit
25
°C
to
-55°C
95
19
16
75
15
13
10
≤85°C
120
24
20
95
19
16
10
≤125°C
145
29
25
110
22
19
10
Unit
ns
t
TLH
, t
THL
ns
C
IN
pF
Power Dissipation Capacitance (Per Inverter)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
Typical @25°C,V
CC
=5.0 V
22
pF
Figure 1. Switching Waveforms
Figure 2. Test Circuit
SLS
System Logic
Semiconductor
