SL74HC161
Presettable Counters
High-Performance Silicon-Gate CMOS
The SL74HC161 is identical in pinout to the LS/ALS161. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC161 is programmable 4-bit synchronous counter that
feature parallel Load, asynchronous Reset, a Carry Output for
cascading and count-enable controls.
The SL74HC161 is binary counter with asynchronous Reset.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
ORDERING INFORMATION
SL74HC161N Plastic
SL74HC161D SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
PIN 16 =V
CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Reset
L
H
H
H
H
H
Load
X
L
H
H
H
X
Enable
P
X
X
X
L
H
X
Enable
T
X
X
L
X
H
X
Clock
X
Q0
L
P0
Outputs
Q1
L
P1
Q2
L
P2
Q3
L
P3
Function
Reset to “0”
Preset Data
No count
No count
Count
No count
No change
No change
Count up
No change
X=don’t care
P0,P1,P2,P3 = logic level of Data inputs
Ripple Carry Out = Enable T
•
Q0
•
Q1
•
Q2
•
Q3
SLS
System Logic
Semiconductor
SL74HC161
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC161
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
≤85
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
40
≤125
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
µA
µA
V
Unit
V
IH
Minimum High-Level
Input Vo ltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
6.0 mA
I
OUT
≤
7.8 mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
IL
V
V
OH
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
6.0 mA
I
OUT
≤
7.8 mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
SLS
System Logic
Semiconductor
SL74HC161
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
f
max
Parameter
Maximum Clock Frequency (Figures 1,6)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
Guaranteed Limit
25
°C
to
-55°C
6
30
35
120
20
16
145
22
18
145
20
17
110
16
14
135
18
15
120
22
18
145
22
20
155
22
18
75
15
13
10
≤85°C
5
24
28
160
23
20
185
25
20
185
22
19
150
18
15
175
20
16
160
27
22
185
28
24
190
26
22
95
19
16
10
≤125°C
4
20
24
200
28
22
320
30
23
220
25
21
190
20
17
210
22
20
200
30
25
220
35
28
230
30
25
110
22
19
10
Unit
MHz
t
PLH
Maximum Propagation Delay Clock to Q
t
PHL
(Figures 1,6)
ns
ns
t
PHL
Maximum Propagation Delay Reset to Q
(Figures 2 and 6)
ns
t
PLH
Maximum Propagation Delay Enable T to Ripple
Carry Out
t
PHL
(Figures 3,6)
ns
ns
t
PLH
Maximum Propagation Delay Clock to Ripple
t
PHL
Carry Out (Figures 1,6)
ns
ns
t
PHL
Maximum Propagation Delay Reset to Ripple Carry
Out (Figures 2,6)
Maximum Output Transition Time, Any Output
(Figures 1 and 6)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Gate)
ns
t
TLH
, t
THL
ns
C
IN
pF
Typical @25°C,V
CC
=5.0 V
30
pF
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
SLS
System Logic
Semiconductor
SL74HC161
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
SU
Parameter
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 4)
Minimum Setup Time, Load to Clock
(Figure 4)
Minimum Setup Time, Enable T or Enable P to
Clock (Figure 5)
Minimum Hold Time, Clock to Load or Preset Data
Inputs (Figure 4)
Minimum Hold Time, Clock to Enable T or Enable
P (Figure 5)
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
Minimum Recovery Time, Load Inactive to Clock
(Figure 4)
Minimum Pulse Width, Clock (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
25
°C
to
-55°C
40
15
12
60
15
12
80
20
17
3
3
3
3
3
3
80
15
12
80
15
12
60
12
10
60
12
10
1000
500
400
≤85°C
60
20
18
75
20
18
95
25
23
3
3
3
3
3
3
95
20
17
95
20
17
75
15
13
75
15
13
1000
500
400
≤125°C
80
30
20
90
30
20
110
35
25
3
3
3
3
3
3
110
26
23
110
26
23
90
18
15
90
18
15
1000
500
400
Unit
ns
t
SU
ns
t
SU
ns
t
h
ns
t
h
ns
t
rec
ns
t
rec
ns
t
w
ns
t
w
Minimum Pulse Width, Reset (Figure 2)
ns
t
r,
t
f
Maximum Input Rise and Fall Times
(Figure 1)
ns
SLS
System Logic
Semiconductor
