DUAL DECADE COUNTER;
DUAL 4-STAGE
BINARY COUNTER
The SN54 / 74LS390 and SN54 / 74LS393 each contain a pair of high-speed
4-stage ripple counters. Each half of the LS390 is partitioned into a
divide-by-two section and a divide-by five section, with a separate clock input
for each section. The two sections can be connected to count in the 8.4.2.1
BCD code or they can count in a biquinary sequence to provide a square wave
(50% duty cycle) at the final output.
Each half of the LS393 operates as a Modulo-16 binary divider, with the last
three stages triggered in a ripple fashion. In both the LS390 and the LS393,
the flip-flops are triggered by a HIGH-to-LOW transition of their CP inputs.
Each half of each circuit type has a Master Reset input which responds to a
HIGH signal by forcing all four outputs to the LOW state.
SN54/74LS390
SN54/74LS393
DUAL DECADE COUNTER;
DUAL 4-STAGE
BINARY COUNTER
LOW POWER SCHOTTKY
•
•
•
•
•
Dual Versions of LS290 and LS293
LS390 has Separate Clocks Allowing
÷
2,
÷
2.5,
÷
5
Individual Asynchronous Clear for Each Counter
Typical Max Count Frequency of 50 MHz
Input Clamp Diodes Minimize High Speed Termination Effects
J SUFFIX
CERAMIC
CASE 620-09
16
1
16
1
N SUFFIX
PLASTIC
CASE 648-08
CONNECTION DIAGRAM DIP
(TOP VIEW)
SN54 / 74LS390
VCC
16
CP0
15
MR
14
Q0
13
CP1
12
Q1
11
Q2
10
Q3
9
16
1
D SUFFIX
SOIC
CASE 751B-03
J SUFFIX
CERAMIC
CASE 632-08
14
1
1
CP0
2
MR
3
Q0
4
CP1
5
Q1
6
Q2
7
Q3
8
GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
14
1
N SUFFIX
PLASTIC
CASE 646-06
SN54 / 74LS393
VCC
14
CP
13
MR
12
Q0
11
Q1
10
Q2
9
Q3
8
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
1
CP
2
MR
3
Q0
4
Q1
5
Q2
6
Q3
7
GND
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
FAST AND LS TTL DATA
5-544
SN54/74LS390
•
SN54/74LS393
PIN NAMES
CP
CP0
CP1
MR
Q0 – Q3
Clock (Active LOW going edge)
Input to +16 (LS393)
Clock (Active LOW going edge)
Input to
÷
2 (LS390)
Clock (Active LOW going edge)
Input to
÷
5 (LS390)
Master Reset (Active HIGH) Input
Flip-Flop outputs (Note b)
LOADING
(Note a)
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
LOW
1.0 U.L.
1.0 U.L.
1.5 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b)
Temperature Ranges.
FUNCTIONAL DESCRIPTION
Each half of the SN54 / 74LS393 operates in the Modulo 16
binary sequence, as indicated in the
÷
16 Truth Table. The first
flip-flop is triggered by HIGH-to-LOW transitions of the CP
input signal. Each of the other flip-flops is triggered by a
HIGH-to-LOW transition of the Q output of the preceding
flip-flop. Thus state changes of the Q outputs do not occur
simultaneously. This means that logic signals derived from
combinations of these outputs will be subject to decoding
spikes and, therefore, should not be used as clocks for other
counters, registers or flip-flops. A HIGH signal on MR forces
all outputs to the LOW state and prevents counting.
Each half of the LS390 contains a
÷
5 section that is
independent except for the common MR function. The
÷
5
section operates in 4.2.1 binary sequence, as shown in the
÷
5
Truth Table, with the third stage output exhibiting a 20% duty
cycle when the input frequency is constant. To obtain a
÷10
function having a 50% duty cycle output, connect the input
signal to CP1 and connect the Q3 output to the CP0 input; the
Q0 output provides the desired 50% duty cycle output. If the
input frequency is connected to CP0 and the Q0 output is
connected to CP1, a decade divider operating in the 8.4.2.1
BCD code is obtained, as shown in the BCD Truth Table. Since
the flip-flops change state asynchronously, logic signals
derived from combinations of LS390 outputs are also subject
to decoding spikes. A HIGH signal on MR forces all outputs
LOW and prevents counting.
SN54 / 74LS390 LOGIC DIAGRAM (one half shown)
CP1
CP0
CD
MR
K CP
J
Q
CD
K CP
J
Q
CD
K CP
J
Q
CD
K CP
J
Q
Q0
Q1
Q2
Q3
SN54 / 74LS393 LOGIC DIAGRAM (one half shown)
CP
CD
MR
K CP
J
Q
CD
K CP
J
Q
CD
K CP
J
Q
CD
K CP
J
Q
Q0
Q1
Q2
Q3
FAST AND LS TTL DATA
5-545
SN54/74LS390
•
SN54/74LS393
SN54 / 74LS390 BCD
TRUTH TABLE
(Input on CP0; Q0 CP1)
OUTPUTS
COUNT
0
1
2
3
4
5
6
7
8
9
Q3
L
L
L
L
L
L
L
L
H
H
Q2 Q1
L
L
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
Q0
L
H
L
H
L
H
L
H
L
H
COUNT
0
1
2
3
4
SN54/ 74LS390
÷
5
TRUTH TABLE
(Input on CP1)
OUTPUTS
Q3
L
L
L
L
H
Q2 Q1
L
L
H
H
L
L
H
L
H
L
SN54 / 74LS393
TRUTH TABLE
OUTPUTS
COUNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Q3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Q2 Q1
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
Q0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
SN54 / 74LS390
÷
10 (50% @ Q0)
TRUTH TABLE
(Input on CP1, Q3 to CP0)
OUTPUTS
COUNT
0
1
2
3
4
5
6
7
8
9
Q3
L
L
L
L
H
L
L
L
L
H
Q2 Q1
L
L
H
H
L
L
L
H
H
L
L
H
L
H
L
L
H
L
H
L
Q0
L
L
L
L
L
H
H
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
FAST AND LS TTL DATA
5-546
SN54/74LS390
•
SN54/74LS393
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
Output LOW Voltage
74
Input HIGH Current
0.1
MR
IIL
Input LOW Current
CP, CP0
CP1
IOS
ICC
Short Circuit Current (Note 1)
Power Supply Current
– 20
– 0.4
– 1.6
– 2.4
– 100
26
0.35
0.5
20
IIH
V
µA
mA
mA
mA
mA
mA
mA
VCC = MAX
VCC = MAX
VCC = MAX, VIN = 0.4 V
2.7
3.5
0.25
0.4
V
V
2.5
– 0.65
3.5
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
fMAX
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Parameter
Maximum Clock Frequency
CP0 to Q0
Maximum Clock Frequency
CP1 to Q1
Propagation Delay,
CP to Q0
CP0 to Q0
CP to Q3
CP0 to Q2
CP1 to Q1
CP1 to Q2
CP1 to Q3
MR to Any Output
LS393
LS390
LS393
LS390
LS390
LS390
LS390
LS390/393
Min
25
20
12
13
12
13
40
40
37
39
13
14
24
26
13
14
24
20
20
20
20
60
60
60
60
21
21
39
39
21
21
39
Typ
35
Max
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
CL = 15 pF
FAST AND LS TTL DATA
5-547
SN54/74LS390
•
SN54/74LS393
AC SETUP REQUIREMENTS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
tW
tW
tW
tW
trec
Parameter
Clock Pulse Width
CP0 Pulse Width
CP1 Pulse Width
MR Pulse Width
Recovery Time
LS393
LS390
LS390
LS390/393
LS390/393
Min
20
20
40
20
25
Typ
Max
Unit
ns
ns
ns
ns
ns
VCC = 5.0 V
Test Conditions
AC WAVEFORMS
*CP
1.3 V
tPHL
1.3 V
tW
1.3 V
tPLH
1.3 V
Q
Figure 1
MR & MS
1.3 V
CP
tPHL
Q
1.3 V
tW
1.3 V
trec
1.3 V
Figure 2
*The number of Clock Pulses required between tPHL and tPLH measurements can be determined from the appropriate Truth Table.
FAST AND LS TTL DATA
5-548
FPGA/CPLD
