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SN74LVC1G34
SINGLE BUFFER GATE
www.ti.com
SCES519F – DECEMBER 2003 – REVISED OCTOBER 2005
FEATURES
•
•
•
•
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 3.5 ns at 3.3 V
Low Power Consumption, 1-µA Max I
CC
±24-mA
Output Drive at 3.3 V
•
•
•
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DRL PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
NC
A
GND
1
5
V
CC
NC
A
1
2
3
5
V
CC
NC
A
1
2
3
5
V
CC
Y
2
GND
4
4
Y
GND
4
3
Y
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
YZV PACKAGE
(BOTTOM VIEW)
GND
A
DNU
3 4
2
1 5
Y
V
CC
GND
A
2 3
1 4
Y
V
CC
DNU − Do not use
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single buffer gate is designed for 1.65-V to 5.5-V V
CC
operation. The SN74LVC1G34 performs the Boolean
function Y = A in positive logic.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
SN74LVC1G34
SINGLE BUFFER GATE
SCES519F – DECEMBER 2003 – REVISED OCTOBER 2005
www.ti.com
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZV
(Pb-free)
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
(1)
(2)
Reel of 3000
SN74LVC1G34YZPR
____
C9
C34_
ORDERABLE PART NUMBER
SN74LVC1G34YEPR
_ _ _C9_
TOP-SIDE MARKING
(2)
–40°C to 85°C
Reel of 3000
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
SN74LVC1G34YZVR
SN74LVC1G34DBVR
SN74LVC1G34DBVT
SN74LVC1G34DCKR
SN74LVC1G34DCKT
SN74LVC1G34DRLR
C9_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YEP, YZA/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
•
= Pb-free).
YZV: The actual top-side marking is on two lines. Line 1 has four characters to denote year, month, day, and assembly/test site. Line 2
has two characters which show the family and function code. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
•
= Pb-free).
FUNCTION TABLE
INPUT
A
H
L
OUTPUT
Y
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)
(DBV, DCK, DRL, YEA, YEP, YZA, and YZP Package)
A
2
4
Y
LOGIC DIAGRAM (POSITIVE LOGIC)
(YZV Package)
A
1
3
Y
2
www.ti.com
SN74LVC1G34
SINGLE BUFFER GATE
SCES519F – DECEMBER 2003 – REVISED OCTOBER 2005
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
Supply voltage range
Input voltage range
Voltage range applied to any output in the high-impedance or power-off state
(2)
Voltage range applied to any output in the high or low
Input clamp current
Output clamp current
Continuous output current
Continuous current through V
CC
or GND
DBV package
DCK package
θ
JA
Package thermal impedance
(4)
DRL package
YEA/YZA package
YEP/YZP package
YZV package
T
stg
(1)
(2)
(3)
(4)
Storage temperature range
–65
state
(2) (3)
V
I
< 0
V
O
< 0
–0.5
–0.5
–0.5
–0.5
MAX
6.5
6.5
6.5
V
CC
+ 0.5
–50
–50
±50
±100
206
252
142
154
132
116
150
°C
°C/W
UNIT
V
V
V
V
mA
mA
mA
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of V
CC
is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
3
SN74LVC1G34
SINGLE BUFFER GATE
SCES519F – DECEMBER 2003 – REVISED OCTOBER 2005
www.ti.com
Recommended Operating Conditions
(1)
MIN
V
CC
Supply voltage
Operating
Data retention only
V
CC
= 1.65 V to 1.95 V
V
IH
High-level input voltage
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
CC
= 1.65 V to 1.95 V
V
IL
Low-level input voltage
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
I
V
O
Input voltage
Output voltage
V
CC
= 1.65 V
V
CC
= 2.3 V
I
OH
High-level output current
V
CC
= 3 V
V
CC
= 4.5 V
V
CC
= 1.65 V
V
CC
= 2.3 V
I
OL
Low-level output current
V
CC
= 3 V
V
CC
= 4.5 V
V
CC
= 1.8 V
±
0.15 V, 2.5 V
±
0.2 V
∆t/∆v
T
A
(1)
Input transition rise or fall rate
Operating free-air temperature
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5 V
±
0.5 V
–40
0
0
1.65
1.5
0.65
×
V
CC
1.7
2
0.7
×
V
CC
0.35
×
V
CC
0.7
0.8
0.3
×
V
CC
5.5
V
CC
–4
–8
–16
–24
–32
4
8
16
24
32
20
10
10
85
°C
ns/V
mA
mA
V
V
V
V
MAX
5.5
UNIT
V
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
4
