SP6330, SP6332
and SP6334
Quad
µPower
Supervisory Circuits
with Manual Reset & Watchdog
FEATURES
■
Low operating voltage of 1.6V
■
Low operating current of 20µA typical
■
Monitors up to four supplies simultaneously
■
Adjustable inputs monitor down to 0.5V
■
Reset asserted down to 0.9V
■
2% accuracy over temperature range
■
Open Drain (OD) or CMOS RSTB output or
CMOS RST output
■
4 Reset Timeout Periods:
50ms, 100ms, 200ms and 400ms
■
Watch Dog Input Functionality -- WDI
■
Manual Reset Input (Active Low) -- MRIB
■
8 Pin TSOT package
V1
V2
MRIB
1
2
3
8
RSTB
7
WDI
6
GND
5
SP6330
8 Pin TSOT
V3
4
V4
Open Drain RESET
SEE PAGE 2 FOR OTHER
AVAILABLE PINOUTS
Available in Lead Free Packaging
DESCRIPTION
SP6330-SP6332- SP6334 Quad Power Supervisory Circuit Family is a family of
microprocessor reset supervisory circuits with multiple reset voltages. The family provides
low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds
and two user defined custom thresholds. These circuits perform a single function: if any of
the input supply voltages drops below its associated threshold, reset outputs are asserted.
The SP6330, SP6332, and SP6334 are packaged in an 8-pin TSOT package. All devices are
fully specified over -40
o
C to +85
o
C temperature range.
TYPICAL APPLICATION CIRCUIT
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
1
PINOUT DIAGRAMS
1
2
3
8
RSTB
7
WDI
V1
V2
MRIB
SP6330
8 Pin TSOT
V1
V2
1
2
3
SP6332
8 Pin TSOT
8
RSTB
7
WDI
V1
V2
1
2
3
SP6334
8 Pin TSOT
8
RST
7
WDI
6
GND
5
6
GND
MRIB
5
6
GND
MRIB
5
V3
4
V4
V3
4
V4
V3
4
V4
Open Drain RESET
CMOS RESET
CMOS RESET
PART
NUMBER
SP6330
SP6332
SP6334
V1
√
√
√
V2
√
√
√
V3
√
√
√
V4
√
√
√
Reset
OD Active Low
CMOS Active Low
CMOS Active High
MRIB
√
√
√
WDI
√
√
√
Feature and Pinout Diagram
Representative Samples Available
Sipex
Product
SP6330
SP6330
SP6330
SP6332
Product
Description
Quad Supervisor
Open Drain low
Quad Supervisor
Open Drain low
Quad Supervisor
Open Drain low
Quad Supervisor
CMOS low
Package
8 Pin TSOT
8 Pin TSOT
8 Pin TSOT
8 Pin TSOT
V1
(Volts)
V2
(Volts)
V3
(Volts)
V4
(Volts)
Reset
(ms)
Ordering #
SP6330EK1-L-W-G-C
SP6330EK1-L-X-J-C
SP6330EK1-L-Z-J-C
SP6330EK1-L-V-G-C
2.925
3.075
4.625
2.625
1.575
2.313
2.313
1.575
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
200
200
200
200
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability
and cause permanent damage to the device.
Terminal Voltage (with respect to GND)
V1, V2..................................................... -0.3 to +6V
Open-Drain RSTB.......................................-0.3 to +6V
CMOS RST, RSTB, ..................... -0.3 to (V1+0.3V)
Input Current/Output
Current..................................,,........................20mA
V3, V4, MRIB, WDI........................-0.3 to (V1+0.3V)
Operating Temperature
Range...............................................-40°Cto +85
°C
Storage Temperature
Range...............................................-65°C to 150°C
Thermal Resistance O
JA
.............................134°C/W
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
2
ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Voltage
Range
Supply Current
MIN
0.9
TYP
MAX
5.5
UNITS
V
uA
CONDITIONS
T
A
= -40ºC to +85ºC
V1 < 5.5V, V2 < 3.60V, all I/O
pins open
V1 < 3.6V, V2 < 2.75V, all I/O
pins open
Z (valid for V1 falling)
Y (valid for V1 falling)
X (valid for V1 falling)
W (valid for V1 falling)
V (valid for V1 falling)
U (valid for V1 falling)
T (valid for V1 falling)
S (valid for V1 falling)
R (valid for V1 falling)
J (valid for V2 falling)
I (valid for V2 falling)
H (valid for V2 falling)
G (valid for V2 falling)
F (valid for V2 falling)
E (valid for V2 falling)
D (valid for V2 falling)
C (valid for V2 falling)
B (valid for V2 falling)
A (valid for V2 falling)
V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
20
15
4.532
4.287
3.013
2.866
2.572
2.273
2.146
1.636
1.548
2.266
2.144
1.631
1.543
1.360
1.286
1.087
1.029
0.816
0.772
4.625
4.375
3.075
2.925
2.625
2.320
2.190
1.670
1.580
2.313
2.188
1.665
1.575
1.388
1.313
1.110
1.050
0.833
0.788
0.06
0.04
0.65
0.5
50
50
37
74
148
296
50
100
200
400
30
25
4.718
4.463
3.137
2.984
2.678
2.367
2.234
1.704
1.612
2.360
2.232
1.698
1.607
1.416
1.340
1.133
1.071
0.850
0.804
V1 Reset
Threshold
V
V2 Reset
Threshold
V
Threshold 1
Tempco
Threshold 2
Tempco
Threshold 1
Hysteresis
Threshold 2
Hysteresis
V1 to RST/RSTB
Delay
V2 to RST/RSTB
Delay
Reset Timeout
Period (T1)
Reset Timeout
Period (T2)
Reset Timeout
Period (T3)
Reset Timeout
Period (T4)
Nov20-06 Rev M
mV/ºC
mV/ºC
%
%
us
us
63
126
252
504
ms
ms
ms
ms
reference to Vth1 typical
reference to Vth2 typical
V1 = Vth1 to (Vth1-0.1V), Vth1
= 3.075
V2 = Vth2 to (Vth2-0.1V), Vth2
= 1.575
TOPT-1
TOPT-2
TOPT-3
TOPT-4
© Copyright 2006 Sipex Corporation
SP6330/32/34 Quad Power Supervisory Circuit Family
3
ELECTRICAL CHARACTERISTICS
PARAMETER
MIN
TYP
500
1.5
500
1.5
MAX
510
50
UNITS
CONDITIONS
V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
V3 RESET COMPARATOR INPUT
V3 Input Threshold
490
V3 Input Current
-50
V3 Threshold
Hysteresis
V4 RESET COMPARATOR INPUT
V4 Input Threshold
490
-50
V4 Input Current
V4 Threshold
Hysteresis
MRIB - MANUAL RESET INPUT
MRIB Input
Threshold
MRIB Input
0.8*V1
Threshold
MRIB Minimum
1
Input Pulse Width
MRIB Glitch
Rejection
MRIB to RST/RSTB
Delay
MRIB Pull-Up
30
Resistance
WDI - WATCHDOG INPUT
Watchdog Timeout
1.3
Period
WDI Pulse Width
0.1
WDI Input
Threshold
WDI Input
0.8*V1
Threshold
WDI Input Current
-500
RESET OUTPUTS RST / RSTB
RSTB
(CMOS or OD)
RSTB (CMOS)
RST (CMOS)
RST (CMOS)
RSTB Output OD
Leakage Current
0.8*V1
0.8*V1
mV
nA
mV
T
A
= +25ºC
510
50
mV
nA
mV
T
A
= +25ºC
0.2*V1
V
V
us
Vil
Vih
150
100
55
85
ns
ns
kΩ
1.6
1.9
sec
us
0.2*V1
V
V
Vil
Vih
WDI = 0.0V or V1
V1 = Vth1 - 0.1V, Isink = 1mA,
output asserted
V1 = Vth1 + 0.1V, Isource =
1mA, output not asserted
V1 = Vth1 - 0.1V, Isource =
1mA, output asserted
V1 = Vth1 + 0.1V, V2 > Vth2,
V3 > 0.5, V4 > 0.5, Isource =
1mA, output not asserted
T
A
= +25ºC
500
0.2*V1
nA
V
V
V
0.2*V1
2
V
nA
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
4
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
Name
V1
V2
MRIB
V3
V4
GND
Description
First supply voltage input. Also powers internal circuitry. Trip threshold
voltage internally set.
Second supply voltage input. Trip threshold voltage internally set.
Manual Reset Input pin. Active low. It has an internal pull-up resistor.
Reset asserted when MRIB is pulled low and is kept asserted for
200ms after MRIB is released or pulled high. Leave open if not used.
Input for the third supply voltage. Trip threshold is 0.5V.
Input for the fourth supply voltage. Trip threshold is 0.5V.
Common ground reference pin.
Watch-Dog Input pin. When no transition is detected at the WDI pin for
the duration of WDI timeout period, reset is asserted. Leave open if
not used. RST/RSTB output is used to signal watchdog timeout
overflow. RST/RSTB output pulses high/low (depending on the active
reset polarity) for the reset timeout period after each watchdog timeout
overflow. The watchdog timer clears whenever the reset is asserted
or manual reset is asserted or a transition is observed at WDI pin.
Watchdog timer functionality can be disabled in parts by leaving this
input floating.
Reset output. Open-Drain or CMOS, active high or low. Reset is
asserted when any of the four supply inputs is below its trip threshold.
It stays asserted for 200 ms (typical / default) after the last supply input
traverses its trip threshold. Reset is guaranteed to be in the correct
state for V1>0.9V. RST/RSTB asserts when V1 or V2 or V3 or V4 drop
below their corresponding reset thresholds, or MRIB is pulled
“LOW” or the watchdog timer triggers a reset (devices without
WDOB). RST/RSTB remains asserted for the reset timeout period
after V1 and V2 and V3 and V4 exceed their corresponding reset
thresholds or MRIB goes “LOW” to “HIGH”. Open-drain outputs
require an external pull-up resistor. CMOS outputs are referenced to
V1.
7
WDI
8
RST/RSTB
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
5
FPGA/CPLD
