SSP45N20B/SSS45N20B
November 2001
SSP45N20B/SSS45N20B
200V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters,
switch mode power supplies, DC-AC converters for
uninterrupted power supply and motor control.
Features
•
•
•
•
•
•
35A, 200V, R
DS(on)
= 0.065Ω @V
GS
= 10 V
Low gate charge ( typical 133 nC)
Low Crss ( typical 120 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
D
G
G DS
TO-220
SSP Series
GD S
TO-220F
SSS Series
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
T
J
, T
STG
T
L
T
C
= 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (T
C
= 25°C)
Drain Current
- Continuous (T
C
= 100°C)
Drain Current
- Pulsed
(Note 1)
SSP45N20B
200
35
22.2
140
±
30
(Note 2)
(Note 1)
(Note 1)
(Note 3)
SSS45N20B
35 *
22.2 *
140 *
650
35
17.6
5.5
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
C
= 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
176
1.41
-55 to +150
300
57
0.45
* Drain current limited by maximum junction temperature.
Thermal Characteristics
Symbol
R
θJC
R
θCS
R
θJA
Parameter
Thermal Resistance, Junction-to-Case Max.
Thermal Resistance, Case-to-Sink Typ.
Thermal Resistance, Junction-to-Ambient Max.
SSP45N20B
0.71
0.5
62.5
SSS45N20B
2.2
--
62.5
Units
°C/W
°C/W
°C/W
©2001 Fairchild Semiconductor Corporation
Rev. A, November 2001
SSP45N20B/SSS45N20B
Electrical Characteristics
Symbol
Parameter
T
C
= 25°C unless otherwise noted
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
∆BV
DSS
/
∆T
J
I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
V
GS
= 0 V, I
D
= 250
µA
I
D
= 250
µA,
Referenced to 25°C
V
DS
= 200 V, V
GS
= 0 V
V
DS
= 160 V, T
C
= 125°C
V
GS
= 30 V, V
DS
= 0 V
V
GS
= -30 V, V
DS
= 0 V
200
--
--
--
--
--
--
0.2
--
--
--
--
--
--
10
100
100
-100
V
V/°C
µA
µA
nA
nA
On Characteristics
V
GS(th)
R
DS(on)
g
FS
Gate Threshold Voltage
Static Drain-Source
On-Resistance
Forward Transconductance
V
DS
= V
GS
, I
D
= 250
µA
V
GS
= 10 V, I
D
= 17.5 A
V
DS
= 40 V, I
D
= 17.5 A
(Note 4)
2.0
--
--
--
0.052
36
4.0
0.065
--
V
Ω
S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
--
--
--
3300
460
120
4300
600
155
pF
pF
pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 160 V, I
D
= 45 A,
V
GS
= 10 V
(Note 4, 5)
V
DD
= 100 V, I
D
= 45 A,
R
G
= 25
Ω
(Note 4, 5)
--
--
--
--
--
--
--
45
340
360
270
133
19
67
100
690
730
550
173
--
--
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
Maximum Continuous Drain-Source Diode Forward Current
Maximum Pulsed Drain-Source Diode Forward Current
V
GS
= 0 V, I
S
= 35 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V
GS
= 0 V, I
S
= 45 A,
dI
F
/ dt = 100 A/µs
(Note 4)
--
--
--
--
--
--
--
--
245
2.27
35
140
1.5
--
--
A
A
V
ns
µC
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.8mH, I
AS
= 35A, V
DD
= 50V, R
G
= 25
Ω,
Starting T
J
= 25°C
3. I
SD
≤
45A, di/dt
≤
300A/µs, V
DD
≤
BV
DSS,
Starting T
J
= 25°C
4. Pulse Test : Pulse width
≤
300µs, Duty cycle
≤
2%
5. Essentially independent of operating temperature
©2001 Fairchild Semiconductor Corporation
Rev. A, November 2001
SSP45N20B/SSS45N20B
Typical Characteristics
10
2
I
D
, Drain Current [A]
I
D
, Drain Current [A]
V
GS
15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
Bottom : 5.0 V
Top :
10
2
10
1
10
1
150 C
25 C
-55 C
o
o
o
10
0
10
0
※
Notes :
1. 250μ s Pulse Test
2. T
C
= 25℃
※
Notes :
1. V
DS
= 40V
2. 250μ s Pulse Test
10
-1
10
0
10
1
10
-1
2
4
6
8
10
V
DS
, Drain-Source Voltage [V]
V
GS
, Gate-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
0.30
10
0.25
2
R
DS(ON)
[
Ω
],
Drain-Source On-Resistance
0.20
0.15
V
GS
= 20V
I
DR
, Reverse Drain Current [A]
V
GS
= 10V
10
1
0.10
150℃
25℃
※
Notes :
1. V
GS
= 0V
2. 250μ s Pulse Test
0.05
※
Note : T
J
= 25
℃
0.00
0
35
70
105
140
175
10
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
I
D
, Drain Current [A]
V
SD
, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation with Source Current
and Temperature
10000
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
12
V
DS
= 40V
10
8000
V
DS
= 100V
V
DS
= 160V
V
GS
, Gate-Source Voltage [V]
8
Capacitance [pF]
6000
C
iss
C
oss
6
4000
C
rss
2000
※
Notes :
1. V
GS
= 0 V
2. f = 1 MHz
4
2
※
Note : I
D
= 45 A
0
-1
10
0
10
0
10
1
0
30
60
90
120
150
V
DS
, Drain-Source Voltage [V]
Q
G
, Total Gate Charge [nC]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2001 Fairchild Semiconductor Corporation
Rev. A, November 2001
SSP45N20B/SSS45N20B
Typical Characteristics
(Continued)
1.2
3.0
2.5
BV
DSS
, (Normalized)
Drain-Source Breakdown Voltage
R
DS(ON)
, (Normalized)
Drain-Source On-Resistance
1.1
2.0
1.0
1.5
1.0
0.9
※
Notes :
1. V
GS
= 0 V
2. I
D
= 250
μ
A
0.5
※
Notes :
1. V
GS
= 10 V
2. I
D
= 22.5 A
0.8
-100
-50
0
50
100
o
150
200
0.0
-100
-50
0
50
100
o
150
200
T
J
, Junction Temperature [ C]
T
J
, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs Temperature
Figure 8. On-Resistance Variation
vs Temperature
Operation in This Area
is Limited by R
DS(on)
Operation in This Area
is Limited by R
DS(on)
10
2
100
µ
s
10
µ
s
10
2
10
µ
s
100
µ
s
1 ms
10 ms
100 ms
DC
I
D
, Drain Current [A]
1 ms
10
1
I
D
, Drain Current [A]
10 ms
DC
10
1
10
0
10
0
※
Notes :
1. T
C
= 25 C
o
2. T
J
= 150 C
3. Single Pulse
o
10
-1
※
Notes :
1. T
C
= 25 C
o
2. T
J
= 150 C
3. Single Pulse
o
10
-1
10
0
10
1
10
2
10
-2
V
DS
, Drain-Source Voltage [V]
10
0
10
1
10
2
V
DS
, Drain-Source Voltage [V]
Figure 9-1. Maximum Safe Operating Area
for SSP45N20B
Figure 9-2. Maximum Safe Operating Area
for SSS45N20B
40
35
30
I
D
, Drain Current [A]
25
20
15
10
5
0
25
50
75
100
125
150
T
C
, Case Temperature [
℃
]
Figure 10. Maximum Drain Current
vs Case Temperature
©2001 Fairchild Semiconductor Corporation
Rev. A, November 2001
SSP45N20B/SSS45N20B
Typical Characteristics
(Continued)
10
0
(t), T h e r m a l R e s p o n s e
D = 0 .5
※
N o te s :
1 . Z
θ
J C
(t) = 0 .7 1
℃
/W M a x .
2 . D u ty F a c to r, D = t
1
/t
2
3 . T
J M
- T
C
= P
D M
* Z
θ
J C
(t)
0 .2
10
-1
0 .1
0 .0 5
0 .0 2
0 .0 1
s in g le p u ls e
P
DM
t
1
t
2
Z
θ
JC
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t
1
, S q u a re W a v e P u ls e D u ra tio n [s e c ]
Figure 11-1. Transient Thermal Response Curve to SSP45N20B
(t), T h e r m a l R e s p o n s e
10
0
D = 0 .5
0 .2
0 .1
※
N o te s :
1 . Z
θ
J C
(t) = 2 .2
℃
/W M a x .
2 . D u ty F a c to r, D = t
1
/t
2
3 . T
J M
- T
C
= P
D M
* Z
θ
J C
(t)
10
-1
0 .0 5
0 .0 2
0 .0 1
s in g le p u ls e
P
DM
t
1
t
2
Z
θ
JC
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t
1
, S q u a re W a v e P u ls e D u ra tio n [s e c ]
Figure 11-2. Transient Thermal Response Curve SSS45N20B
©2001 Fairchild Semiconductor Corporation
Rev. A, November 2001
