SST25VF016B
16 Mbit SPI Serial Flash
Features
• Single Voltage Read and Write Operations
- 2.7-3.6V
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
- Up to 50 MHz
• Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read Current: 10 mA (typical)
- Standby Current: 5 µA (typical)
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 32 KByte overlay blocks
- Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
- Chip-Erase Time: 35 ms (typical)
- Sector-/Block-Erase Time: 18 ms (typical)
- Byte-Program Time: 7 µs (typical)
• Auto Address Increment (AAI) Programming
- Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
- Software polling the BUSY bit in Status Register
- Busy Status readout on SO pin in AAI Mode
• Hold Pin (HOLD#)
- Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
- Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
- Write protection through Block-Protection bits in
status register
• Temperature Range
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
• Packages Available
- 8-lead SOIC (200 mils)
- 8-contact WSON (6mm x 5mm)
• All devices are RoHS compliant
Product Description
The 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ulti-
mately lowers total system costs. The SST25VF016B
devices are enhanced with improved operating fre-
quency and even lower power consumption than the
original SST25VFxxxA devices. SST25VF016B SPI
serial flash memories are manufactured with propri-
etary, high-performance CMOS SuperFlash technol-
ogy. The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches.
SST25VF016B devices significantly improve perfor-
mance and reliability, while lowering power consump-
tion. The devices write (Program or Erase) with a single
power supply of 2.7-3.6V for SST25VF016B. The total
energy consumed is a function of the applied voltage,
current, and time of application. Since for any given
voltage range, the SuperFlash technology uses less
current to program and has a shorter erase time, the
total energy consumed during any Erase or Program
operation is less than alternative flash memory technol-
ogies.
The SST25VF016B device is offered in both 8-lead
SOIC (200 mils) and 8-contact WSON (6mm x 5mm)
packages. See
Figure 2-1
for pin assignments.
2015 Microchip Technology Inc.
DS20005044C-page 1
SST25VF016B
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The
last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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DS20005044C-page 2
2015 Microchip Technology Inc.
SST25VF016B
1.0
BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
FIGURE 1-1:
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
CE#
SCK
SI
SO
WP#
HOLD#
1271 B1.0
2015 Microchip Technology Inc.
DS20005044C-page 3
SST25VF016B
2.0
PIN DESCRIPTION
PIN ASSIGNMENTS
1
2
8
7
FIGURE 2-1:
CE#
SO
WP#
VSS
VDD
HOLD#
SCK
SI
CE#
SO
WP#
VSS
1
8
VDD
HOLD#
SCK
SI
2
7
Top View
3
4
6
5
3
Top View
6
4
5
1271 08-wson QA P2.0
1271 08-soic S2A P1.0
8-Lead SOIC
8-Contact WSON
TABLE 2-1:
SCK
PIN DESCRIPTION
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#
pin. See
“Hardware End-of-Write Detection” on page 11
for details.
The device is enabled by a high to low transition on CE#. CE# must remain low for
the duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the
device.
To provide power supply voltage: 2.7-3.6V for SST25VF016B
Symbol Pin Name
Serial Clock
SI
SO
Serial Data Input
Serial Data Output
CE#
WP#
HOLD#
V
DD
V
SS
Chip Enable
Write Protect
Hold
Power Supply
Ground
DS20005044C-page 4
2015 Microchip Technology Inc.
SST25VF016B
3.0
MEMORY ORGANIZATION
used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
The SST25VF016B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in
Figure 4-1,
is the
state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sam-
pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
The SST25VF016B SuperFlash memory array is orga-
nized in uniform 4 KByte erasable sectors with
32 KByte overlay blocks and 64 KByte overlay eras-
able blocks.
4.0
DEVICE OPERATION
The SST25VF016B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is
FIGURE 4-1:
CE#
MODE 3
SPI PROTOCOL
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1271 SPIprot.0
HIGH IMPEDANCE
4.1
Hold Operation
The HOLD# pin is used to pause a serial sequence
underway with the SPI flash memory without resetting
the clocking sequence. To activate the HOLD# mode,
CE# must be in active low state. The HOLD# mode
begins when the SCK active low state coincides with
the falling edge of the HOLD# signal. The HOLD mode
ends when the HOLD# signal’s rising edge coincides
with the SCK active low state.
If the falling edge of the HOLD# signal does not coin-
cide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the
active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active
low state, then the device exits in Hold mode when the
SCK next reaches the active low state. See
Figure 4-2
for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be V
IL
or V
IH.
If CE# is driven active high during a Hold condition, it
resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold
condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be
driven active low. See
Figure 5-3
for Hold timing.
FIGURE 4-2:
SCK
HOLD CONDITION WAVEFORM
HOLD#
Active
Hold
Active
Hold
Active
1271 HoldCond.0
4.2
Write Protection
SST25VF016B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protec-
tion bits (BP3, BP2, BP1, BP0, and BPL) in the status
register provide Write protection to the memory array
and the status register. See
Table 4-3
for the Block-Pro-
tection description.
2015 Microchip Technology Inc.
DS20005044C-page 5
