SST25WF080B
8 Mbit 1.8V SPI Serial Flash
Features
• Single Voltage Read and Write Operations
- 1.65-1.95V
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
- 40MHz
• Dual Input/Output Support
- Fast-Read Dual-Output Instruction (3BH)
- Fast-Read Dual I/O Instruction (BBH)
• Superior Reliability
- Endurance: 100,000 Cycles
- Greater than 20 years Data Retention
• Ultra-Low Power Consumption:
- Active Read Current: 4 mA (typical)
- Standby Current: 10 µA (typical)
- Power-down Mode Standby Current: 4 µA (typical)
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 64 KByte overlay blocks
• Page Program Mode
- 256 Bytes/Page
• Fast Erase and Page-Program:
- Chip-Erase Time: 500 ms (typical)
- Sector-Erase Time: 40 ms (typical)
- Block-Erase Time: 80 ms (typical)
- Page-Program Time: 0.8 ms/ 256 bytes (typical)
• End-of-Write Detection
- Software polling the BUSY bit in Status Register
• Hold Pin (HOLD#)
- Suspend a serial sequence without deselect-
ing the device
• Write Protection (WP#)
- Enables/Disables the Lock-Down function of
the status register
• Software Write Protection
- Write protection through Block-Protection bits
in status register
• Temperature Range
- Industrial: -40°C to +85°C
• Packages Available
- 8-lead SOIC (150 mils)
- 8-contact USON (2mm x 3mm)
• All devices are RoHS compliant
Product Description
SST25WF080B is a member of the Serial Flash 25
Series family and feature a four-wire, SPI-compatible
interface that allows for a low pin-count package which
occupies less board space and ultimately lowers total
system costs. SPI serial flash memory is manufactured
with proprietary, high-performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide
tunneling injector attain better reliability and manufac-
turability compared with alternate approaches.
This Serial Flash significantly improve performance
and reliability, while lowering power consumption. The
device writes (Program or Erase) with a single power
supply of 1.65-1.95V. The total energy consumed is a
function of the applied voltage, current, and time of
application. Since for any given voltage range, the
SuperFlash technology uses less current to program
and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less
than alternative flash memory technologies.
SST25WF080B is offered in 8-lead SOIC and 8-contact
USON packages. See
Figure 2-1
for the pin assign-
ments.
2013-2017 Microchip Technology Inc.
DS20005164D-page 1
SST25WF080B
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-
mail at
docerrors@microchip.com.
We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The
last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site;
http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at
www.microchip.com
to receive the most current information on all of our products.
2013-2017 Microchip Technology Inc.
DS20005164D-page 2
SST25WF080B
1.0
FUNCTIONAL BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
FIGURE 1-1:
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
CE#
SCK
SI/ SO/ WP#
SIO0 SIO1
HOLD#
25164 F01.0
2013-2017 Microchip Technology Inc.
DS20005164D-page 3
SST25WF080B
2.0
PIN DESCRIPTION
PIN ASSIGNMENTS
FIGURE 2-1:
CE#
SO/SIO1
WP#
V
SS
1
2
3
4
8
7
6
5
V
DD
HOLD#
SCK
SI/SIO0
25164 08-soic-P0.0
CE#
SO/SIO1
WP#
VSS
1
8
VDD
HOLD#
SCK
SI/SIO0
2
Top View
7
3
6
4
5
25164 08-uson Q3A P1.0
8-Lead SOIC
8-Contact USON
TABLE 2-1:
Symbol
SCK
PIN DESCRIPTION
Pin Name
Serial Clock
Functions
To provide the input/output timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
SI
SO
SIO
[0:1]
Serial Data Input
Serial Data Output
Serial Data Input/
To transfer commands, addresses, or data serially into the device, or data out of
Output for Dual I/O the device. Inputs are latched on the rising edge of the serial clock. Data is
Mode
shifted out on the falling edge of the serial clock. These pins are used in Dual
I/O mode
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence. The device is deselected and
placed in Standby mode when CE# is high.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status reg-
ister.
To temporarily stop serial communication with SPI Flash memory while device
is selected.
To provide power supply voltage: 1.65-1.95V for SST25WF080B
CE#
WP#
HOLD#
V
DD
V
SS
Write Protect
Hold
Power Supply
Ground
2013-2017 Microchip Technology Inc.
DS20005164D-page 4
SST25WF080B
3.0
MEMORY ORGANIZATION
The SST25WF080B SuperFlash memory arrays are
organized in 256 uniform 4 KByte sectors, with 16
64 KByte overlay erasable blocks.
FIGURE 3-1:
MEMORY MAP
Number of 64 KByte
Blocks
Number of Sectors
255
15
Top of Memory Block
0FFFFFH
0FF000H
...
240
0F0FFFH
0F0000H
...
...
31
1
01FFFFH
01F000H
...
16
15
01FFFFH
010000H
00FFFFH
00F000H
...
0
1
0
001FFFH
001000H
000FFFH
000000H
Bottom of Memory Block
25164 F51.0
4.0
DEVICE OPERATION
SST25WF080B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is
used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
The SST25WF080B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in
Figure 4-1,
is the
state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sam-
pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
FIGURE 4-1:
CE#
MODE 3
SPI PROTOCOL
...
...
...
...
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
25164 F03.0
HIGH IMPEDANCE
2013-2017 Microchip Technology Inc.
DS20005164D-page 5
