ST1230C..KP Series
www.vishay.com
Vishay Semiconductors
Phase Control Thyristors
(Hockey PUK Version), 1745 A
FEATURES
• Center amplifying gate
• Metal case with ceramic insulator
• International standard case A-24 (K-PUK)
• High profile hockey PUK
• Designed and qualified for industrial level
• Material categorization: For definitions of compliance
please see
www.vishay.com/doc?99912
TYPICAL APPLICATIONS
• DC motor controls
• Controlled DC power supplies
A-24 (K-PUK)
• AC controllers
PRODUCT SUMMARY
I
T(AV)
1745 A
MAJOR RATINGS AND CHARACTERISTICS
PARAMETER
I
T(AV)
I
T(RMS)
I
TSM
I
2
t
V
DRM
/V
RRM
t
q
T
J
Typical
TEST CONDITIONS
VALUES
1745
T
hs
T
hs
50 Hz
60 Hz
50 Hz
60 Hz
55
3200
25
33 500
35 100
5615
5126
800 to 1600
200
- 40 to 125
UNITS
A
°C
A
°C
A
kA
2
s
V
μs
°C
ELECTRICAL SPECIFICATIONS
VOLTAGE RATINGS
TYPE
NUMBER
VOLTAGE
CODE
08
ST1230C..K
12
14
16
V
RSM
, MAXIMUM
V
DRM
/V
RRM
, MAXIMUM REPETITIVE PEAK
AND OFF-STATE VOLTAGE
NON-REPETITIVE PEAK VOLTAGE
V
V
800
1200
1400
1600
900
1300
1500
1700
100
I
DRM
/I
RRM
MAXIMUM
AT T
J
= T
J
MAXIMUM
mA
Revision: 10-Apr-13
Document Number: 94395
1
For technical questions within your region:
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
ST1230C..KP Series
www.vishay.com
Vishay Semiconductors
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Maximum average on-state current
at heatsink temperature
Maximum RMS on-state current
SYMBOL
I
T(AV)
I
T(RMS)
TEST CONDITIONS
180° conduction, half sine wave
double side (single side) cooled
DC at 25 °C heatsink temperature double side cooled
t = 10 ms
Maximum peak, one-cycle
non-repetitive surge current
I
TSM
t = 8.3 ms
t = 10 ms
t = 8.3 ms
t = 10 ms
Maximum I
2
t for fusing
I
2
t
t = 8.3 ms
t = 10 ms
t = 8.3 ms
Maximum I
2
t
for fusing
Low level value of threshold voltage
High level value of threshold voltage
Low level value of on-state slope resistance
High level value of on-state slope resistance
Maximum on-state voltage
Maximum holding current
Typical latching current
I
2
t
V
T(TO)1
V
T(TO)2
r
t1
r
t2
V
TM
I
H
I
L
No voltage
reapplied
100 % V
RRM
reapplied
No voltage
reapplied
100 % V
RRM
reapplied
VALUES
1745 (700)
55 (85)
3200
33 500
35 100
28 200
Sinusoidal half wave,
initial T
J
= T
J
maximum
29 500
5615
5126
3971
3625
56 150
0.93
1.02
0.17
0.16
1.62
600
1000
kA
2
s
V
kA
2
s
A
UNITS
A
°C
t = 0.1 to 10 ms, no voltage reapplied
(16.7 % x
x I
T(AV)
< I <
x I
T(AV)
), T
J
= T
J
maximum
(I >
x I
T(AV)
), T
J
= T
J
maximum
(16.7 % x
x I
T(AV)
< I <
x I
T(AV)
), T
J
= T
J
maximum
(I >
x I
T(AV)
), T
J
= T
J
maximum
I
pk
= 4000 A, T
J
= T
J
maximum, t
p
= 10 ms sine pulse
T
J
= 25 °C, anode supply 12 V resistive load
m
V
mA
SWITCHING
PARAMETER
Maximum non-repetitive rate of
rise of turned-on current
Typical delay time
Typical turn-off time
SYMBOL
dI/dt
t
d
t
q
TEST CONDITIONS
Gate drive 20 V, 20
,
t
r
1 μs
T
J
= T
J
maximum, anode voltage
80 % V
DRM
Gate current 1 A, dI
g
/dt = 1 A/μs
V
d
= 0.67 % V
DRM
, T
J
= 25 °C
I
TM
= 550 A, T
J
= T
J
maximum, dI/dt = 40 A/μs,
V
R
= 50 V, dV/dt = 20 V/μs, gate 0 V 100
,
t
p
= 500 μs
VALUES
1000
1.9
μs
200
UNITS
A/μs
BLOCKING
PARAMETER
Maximum critical rate of rise of
off-state voltage
Maximum peak reverse and
off-state leakage current
SYMBOL
dV/dt
I
RRM
,
I
DRM
TEST CONDITIONS
T
J
= T
J
maximum linear to 80 % rated V
DRM
T
J
= T
J
maximum, rated V
DRM
/V
RRM
applied
VALUES
500
100
UNIT
S
V/μs
mA
Revision: 10-Apr-13
Document Number: 94395
2
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
ST1230C..KP Series
www.vishay.com
Vishay Semiconductors
TRIGGERING
PARAMETER
Maximum peak gate power
Maximum average gate power
Maximum peak positive gate current
Maximum peak positive gate voltage
Maximum peak negative gate voltage
SYMBOL
P
GM
P
G(AV)
I
GM
+ V
GM
- V
GM
T
J
= - 40 °C
DC gate current required to trigger
I
GT
T
J
= 25 °C
T
J
= 125 °C
T
J
= - 40 °C
DC gate voltage required to trigger
V
GT
T
J
= 25 °C
T
J
= 125 °C
DC gate current not to trigger
I
GD
T
J
= T
J
maximum
DC gate voltage not to trigger
V
GD
Maximum gate current/
voltage not to trigger is the
maximum value which will not
trigger any unit with rated V
DRM
anode to cathode applied
Maximum required gate trigger/
current/voltage are the lowest
value which will trigger all units
12 V anode to cathode applied
200
100
50
1.4
1.1
0.9
10
T
J
= T
J
maximum, t
p
5 ms
TEST CONDITIONS
T
J
= T
J
maximum, t
p
5 ms
T
J
= T
J
maximum, f = 50 Hz, d% = 50
VALUES
typ.
16
3
3.0
20
5.0
-
200
-
-
3.0
-
mA
V
mA
Max.
UNITS
W
A
V
0.25
V
THERMAL AND MECHANICAL SPECIFICATIONS
PARAMETER
Maximum operating junction
temperature range
Maximum storage temperature range
Maximum thermal resistance,
junction to heatsink
Maximum thermal resistance,
case to heatsink
Mounting force, ± 10 %
Approximate weight
Case style
See dimensions - link at the end of datasheet
SYMBOL
T
J
T
Stg
R
thJ-hs
R
thC-hs
DC operation single side cooled
DC operation double side cooled
DC operation single side cooled
DC operation double side cooled
TEST CONDITIONS
VALUES
- 40 to 125
- 40 to 150
0.042
0.021
0.006
0.003
24 500
(2500)
425
A-24 (K-PUK)
N
(kg)
g
K/W
UNITS
°C
R
thJC
CONDUCTION
CONDUCTION ANGLE
180°
120°
90°
60°
30°
SINUSOIDAL
CONDUCTION
SINGLE SIDE
0.003
0.004
0.005
0.007
0.012
DOUBLE SIDE
0.003
0.004
0.005
0.007
0.012
RECTANGULAR
CONDUCTION
SINGLE SIDE
0.002
0.004
0.005
0.007
0.012
DOUBLE SIDE
0.002
0.004
0.005
0.007
0.012
T
J
= T
J
maximum
K/W
TEST CONDITIONS
UNITS
Note
• The table above shows the increment of thermal resistance R
thJC
when devices operate at different conduction angles than DC
Revision: 10-Apr-13
Document Number: 94395
3
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
ST1230C..KP Series
www.vishay.com
Vishay Semiconductors
Maximum Allowable Heatsink Temperature
(°C)
130
120
110
100
90
80
70
60
50
40
30
20
0
500 1000 1500 2000 2500 3000 3500
30˚
60˚
90˚
120˚
180˚
DC
Conduction Period
Maximum Allowable Heatsink Temperature
(°C)
130
120
110
100
90
80
70
60
50
40
0
30˚
ST1230C..K Series
(Single Side Cooled)
R
thJ-hs
(DC) = 0.042 K/W
ST1230C..K Series
(Double Side Cooled)
R
thJ-hs
(DC) = 0.021 K/W
Conduction Angle
60˚
90˚
120˚
180˚
200 400 600 800 1000 1200 1400
Average On-state Current (A)
Average On-state Current (A)
Fig. 1 - Current Ratings Characteristics
Fig. 4 - Current Ratings Characteristics
Maximum Allowable Heatsink Temperature
(°C)
130
120
110
100
90
80
70
60
50
40
30
20
0
400
30˚
60˚
Maximum Average On-state Power Loss (W)
ST1230C..K Series
(Single Side Cooled)
R
thJ-hs
(DC) = 0.042 K/W
4000
3500
3000
2500
2000
1500
1000
500
0
0
400
800
1200 1600 2000 2400
ST1230C..K Series
T
J
= 125˚C
Conduction Angle
180˚
120˚
90˚
60˚
30˚
RMS Limit
Conduction Period
90˚
120˚
180˚
DC
800
1200
1600
2000
Average On-state Current (A)
Average On-state Current (A)
Fig. 2 - Current Ratings Characteristics
Fig. 5 - On-State Power Loss Characteristics
130
120
110
100
90
80
70
60
50
40
30
0
500
30˚
Maximum Average On-state Power Loss (W)
Maximum Allowable Heatsink Temperature
(°C)
ST1230C..K Series
(Double Side Cooled)
R
thJ-hs
(DC) = 0.021 K/W
5000
4000
DC
180˚
120˚
90˚
60˚
30˚
Conduction Angle
3000
RMS Limit
2000
60˚
Conduction Period
90˚
120˚
180˚
1000
ST1230C..K Series
T
J
= 125˚C
1000
1500
2000
2500
0
0
500 1000 1500 2000 2500 3000 3500
Average On-state Current (A)
Average On-state Current (A)
Fig. 3 - Current Ratings Characteristics
Fig. 6 - On-State Power Loss Characteristics
Revision: 10-Apr-13
Document Number: 94395
4
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
ST1230C..KP Series
www.vishay.com
Vishay Semiconductors
Peak Half Sine Wave On-state Current (A)
34000
32000
30000
28000
26000
24000
22000
20000
18000
16000
14000
12000
0.01
0.1
1
ST1230C..K Series
Maximum Non Repetitive Surge Current
Versus Pulse Train Duration. Control
Of Conduction May Not Be Maintained.
Initial T
J
= 125˚C
No Voltage Reapplied
Rated V
RRM
Reapplied
Peak Half Sine Wave On-state Current (A)
30000
28000
26000
24000
22000
20000
18000
16000
14000
1
At Any Rated Load Condition And With
Rated V
RRM
Applied Following Surge.
Initial T
J
= 125˚C
@ 60 Hz 0.0083 s
@ 50 Hz 0.0100 s
ST1230C..K Series
10
100
Number Of Equal Amplitude Half Cycle Current Pulses (N)
Pulse Train Duration (s)
Fig. 7 - Maximum Non-Repetitive Surge Current
Single and Double Side Cooled
Fig. 8 - Maximum Non-Repetitive Surge Current
Single and Double Side Cooled
10000
Instantaneous On-state Current (A)
1000
T
J
= 25˚C
T
J
= 125˚C
ST1230C..K Series
100
0.5
1
1.5
2
2.5
3
Instantaneous On-state Voltage (V)
Fig. 9 - On-State Voltage Drop Characteristics
(K/W)
0.1
Steady State Value
R
thJ-hs
= 0.042 K/W
(Single Side Cooled)
R
thJ-hs
= 0.021 K/W
(Double Side Cooled)
Transient Thermal Impedance Z
thJ-hs
0.01
(DC Operation)
ST1230C..K Series
0.001
0.001
0.01
0.1
1
10
100
Square Wave Pulse Duration (s)
Fig. 10 - Thermal Impedance Z
thJ-hs
Characteristics
Revision: 10-Apr-13
Document Number: 94395
5
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
FPGA/CPLD
