ST2047RD410472SE
March 27, 2019
Ordering Information
Part Number
ST2047RD410472SE
Description
2Gx72 (16GB), DDR4, 288-Pin Registered DIMM, Parity,
ECC, 1Gx4 Based, DDR4-2400-17-17-17, 31.25mm,
1.2V, Halogen-Free & RoHS Compliant.
Device Vendor
Samsung, Rev. E
K4A4G045WE-BCRC
(All specifications of this module are subject to change without notice.)
Corporate Headquarters:
39870 Eureka Dr., Newark, CA, 94560, USA • Tel: (510) 623-1231 • Fax: (510) 623-1434 • E-mail: info@smartm.com
Europe:
305 Nasmyth Building, Scottish Enterprise Tech Park, Glasgow, Scotland, G75 0QD, United Kingdom • Tel: (+44) 1355 813455 • Fax: (+44) 1355 813456
Latin America:
Av. Tegula, 888, Edificio Cristal - CEA, Ponte Alta, Atibaia, Sao Paulo, Brazil, 12952-820 • Tel: (+55) 11 4417-7200 • Fax: (+55) 11 4417-7219
Asia:
Plot 18, Lorong Jelawat 4, Kawasan Perindustrian Seberang Jaya, 13700 Perai, Penang, Malaysia • Tel: (+604) 399 2909 • Fax: (+604) 399 2963
©2019 SMART Modular - Confidential
1
ST2047RD410472SE
March 27, 2019
Part Number Decode
S T 204 7 RD4 104 7 2 S E
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1
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3
4
5
6
7
8
9
10
2
3
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SMART Modular Technologies
Module Process Technology
T: RoHS Compliant DDR4 Enterprise
Module Address Depth
204: 2G
Module Data Bus Width
7: x72
Module Configuration
RD4: 1.2V DDR4 288-Pin Registered DIMM
Device Configuration
104: 1Gx4 Based
CAS Latency
7: CL 17
Device Speed
2: DDR4-2400
Device Vendor
S: Samsung
Device Revision
E: Revision E
Corporate Headquarters:
39870 Eureka Dr., Newark, CA, 94560, USA • Tel: (510) 623-1231 • Fax: (510) 623-1434 • E-mail: info@smartm.com
Europe:
305 Nasmyth Building, Scottish Enterprise Tech Park, Glasgow, Scotland, G75 0QD, United Kingdom • Tel: (+44) 1355 813455 • Fax: (+44) 1355 813456
Latin America:
Av. Tegula, 888, Edificio Cristal - CEA, Ponte Alta, Atibaia, Sao Paulo, Brazil, 12952-820 • Tel: (+55) 11 4417-7200 • Fax: (+55) 11 4417-7219
Asia:
Plot 18, Lorong Jelawat 4, Kawasan Perindustrian Seberang Jaya, 13700 Perai, Penang, Malaysia • Tel: (+604) 399 2909 • Fax: (+604) 399 2963
©2019 SMART Modular - Confidential
2
ST2047RD410472SE
March 27, 2019
Revision History
Date
March 27, 2019
Description
Datasheet released.
Corporate Headquarters:
39870 Eureka Dr., Newark, CA, 94560, USA • Tel: (510) 623-1231 • Fax: (510) 623-1434 • E-mail: info@smartm.com
Europe:
305 Nasmyth Building, Scottish Enterprise Tech Park, Glasgow, Scotland, G75 0QD, United Kingdom • Tel: (+44) 1355 813455 • Fax: (+44) 1355 813456
Latin America:
Av. Tegula, 888, Edificio Cristal - CEA, Ponte Alta, Atibaia, Sao Paulo, Brazil, 12952-820 • Tel: (+55) 11 4417-7200 • Fax: (+55) 11 4417-7219
Asia:
Plot 18, Lorong Jelawat 4, Kawasan Perindustrian Seberang Jaya, 13700 Perai, Penang, Malaysia • Tel: (+604) 399 2909 • Fax: (+604) 399 2963
©2019 SMART Modular - Confidential
3
ST2047RD410472SE
March 27, 2019
16GB (2Gx72) DDR4 SDRAM Module - 1Gx4 Based
288-Pin Registered DIMM, Parity, ECC
Features
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Standard = JEDEC
Configuration = ECC
Number of Module Ranks = 2 Ranks
Number of Devices = 36
V
DD
= V
DDQ
= 1.2V
V
PP =
2.5V
V
DDSPD
= 2.25V to 2.75V
Cycle Time = 0.833ns
CAS Latency = 10, 11, 12, 13, 14, 15, 16, 17, 18
CAS Latency with Read DBI = 12, 13, 14, 15, 16,
18, 19, 20, 21
Additive Latency = 0, CL - 1, and CL - 2
CAS Write Latency (CWL) = 9, 10, 11, 12, 14, 16
Burst Length (BL) switch on-the-fly BL8 or BC4
(Burst Chop)
Burst Type = Sequential & Interleave
Bi-Directional Differential Data Strobe
On-Die Termination (ODT)
8 bit pre-fetch
Device Package = FBGA
Lead Finish =
≥
0.76μm Gold
Length x Height = 133.35mm x 31.25mm
No. of sides = Double-sided
Mating Connector (Examples)
Vertical = Vertical = Molex - 0787261002
Vertical = TE Connectivity - 2199154-2
•
Bank Grouping is applied, and CAS to CAS latency
(t
CCD_L
, t
CCD_S
) for the banks in the same or differ-
ent bank group accesses are available
Supports ECC error correction and detection
Temperature sensor with integrated SPD
Per DRAM Addressability is supported
Internal V
REF
DQ level generation is available
Write CRC is supported at all speed grades
CA parity (Command/Address Parity) mode is sup-
ported
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Addressing
Device Configuration
Number of Bank Groups
Bank Groups
Bank Address
Row Address
Column Address
Page size
1Gx4
4
BG0 - BG1
BA0 - BA1
A0 - A15
A0 - A9
512B
Corporate Headquarters:
39870 Eureka Dr., Newark, CA, 94560, USA • Tel: (510) 623-1231 • Fax: (510) 623-1434 • E-mail: info@smartm.com
Europe:
305 Nasmyth Building, Scottish Enterprise Tech Park, Glasgow, Scotland, G75 0QD, United Kingdom • Tel: (+44) 1355 813455 • Fax: (+44) 1355 813456
Latin America:
Av. Tegula, 888, Edificio Cristal - CEA, Ponte Alta, Atibaia, Sao Paulo, Brazil, 12952-820 • Tel: (+55) 11 4417-7200 • Fax: (+55) 11 4417-7219
Asia:
Plot 18, Lorong Jelawat 4, Kawasan Perindustrian Seberang Jaya, 13700 Perai, Penang, Malaysia • Tel: (+604) 399 2909 • Fax: (+604) 399 2963
©2019 SMART Modular - Confidential
4
ST2047RD410472SE
March 27, 2019
Pin Description Table
Symbol
CK0-CK1,
CK0-CK1
Type
Input
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the cross-
ing of the positive edge of CK and negative edge of CK.
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers
and output drivers. Taking CKE Low provides Precharge Power- Down and Self-Refresh operation (all banks
idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After V
REFCA
and Internal DQ V
REF
have become stable during the power on and initialization sequence, they must be main-
tained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers,
excluding CKE, are disabled during Self- Refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection
on systems with multiple Ranks. CS is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4
SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS. The ODT pin will be ignored if MR1 is
programmed to disable RTT_NOM.
Activation Command Input: ACT defines the Activation command being entered along with CS. The input into
RAS/A16, CAS/A15 and WE/A14 will be considered as Row Address A16, A15 and A14.
Command Inputs: RAS/A16, CAS/A15 and WE/A14 (along with CS) define the command being entered.
Those pins have multi function. For example, for activation with ACT Low, those are Addressing like A16, A15
and A14 but for non-activation command with ACT High, those are Command pins for Read, Write and other
command defined in command truth table.
Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write or Precharge command is
being applied. BG0 also determines which mode register is to be accessed during a MRS cycle.
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines which mode register is to be accessed during a MRS cycle.
Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write
commands to select one location out of the memory array in the respective bank. (A10/AP, A12/BC, RAS/A16,
CAS/A15 and WE/A14 have additional functions, see other rows. The address inputs also provide the op-code
during Mode Register Set commands. A17 is connected to the register for the CA parity check.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether Auto-precharge should
be performed to the accessed bank after the Read/Write operation. (HIGH: Auto-precharge; LOW: no Auto-
precharge). A10 is sampled during a Precharge command to determine whether the Precharge applies to one
bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank
addresses.
Burst Chop: A12/BC is sampled during Read and Write commands to determine if burst chop (on-the-fly) will
be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH.
RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at
80% and 20% of V
DD
.
Data Input/Output: Bi-directional data bus. If CRC is enabled via Mode register, then CRC code is added at the
end of Data Burst. Any DQ from DQ0~DQ3 may indicate the internal V
REF
level during test via Mode Register
Setting MR4 A4 = HIGH.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data.
DDR4 SDRAM supports differential data strobe only and does not support single-ended.
CKE0-CKE1
Input
CS0-CS1
Input
ODT0-ODT1
Input
ACT
RAS/A16,
CAS/A15,
WE/A14
BG0-BG1
BA0-BA1
Input
Input
Input
Input
A0-A17
Input
A10/AP
Input
A12/BC
Input
RESET
Input
DQ0-DQ63
CB0-CB7
DQS0-DQS17
DQS0-DQS17
Input/
Output
Input/
Output
Corporate Headquarters:
39870 Eureka Dr., Newark, CA, 94560, USA • Tel: (510) 623-1231 • Fax: (510) 623-1434 • E-mail: info@smartm.com
Europe:
305 Nasmyth Building, Scottish Enterprise Tech Park, Glasgow, Scotland, G75 0QD, United Kingdom • Tel: (+44) 1355 813455 • Fax: (+44) 1355 813456
Latin America:
Av. Tegula, 888, Edificio Cristal - CEA, Ponte Alta, Atibaia, Sao Paulo, Brazil, 12952-820 • Tel: (+55) 11 4417-7200 • Fax: (+55) 11 4417-7219
Asia:
Plot 18, Lorong Jelawat 4, Kawasan Perindustrian Seberang Jaya, 13700 Perai, Penang, Malaysia • Tel: (+604) 399 2909 • Fax: (+604) 399 2963
©2019 SMART Modular - Confidential
5
