ST7LITE1xB
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
DATA EEPROM, ADC, 5 TIMERS, SPI
Memories
– up to 4 Kbytes single voltage extended Flash
(XFlash) Program memory with read-out pro-
tection, In-Circuit Programming and In-Appli-
cation programming (ICP and IAP). 10K write/
erase cycles guaranteed, data retention: 20
years at 55°C.
– 256 bytes RAM
– 128 bytes data EEPROM with read-out pro-
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
■
Clock, Reset and Supply Management
– Enhanced reset system
– Enhanced low voltage supervisor (LVD) for
main supply and an auxiliary voltage detector
(AVD) with interrupt capability for implement-
ing safe power-down procedures
– Clock sources: Internal 1% RC oscillator (on
ST7FLITE15B and ST7FLITE19B), crystal/
ceramic resonator or external clock
– Internal 32-MHz input clock for Auto-reload
timer
– Optional x4 or x8 PLL for 4 or 8 MHz internal
clock
– Five Power Saving Modes: Halt, Active-Halt,
Auto Wake-up from Halt, Wait and Slow
■
I/O Ports
– Up to 17 multifunctional bidirectional I/O lines
– 7 high sink outputs
■
5 Timers
– Configurable watchdog timer
– Two 8-bit Lite Timers with prescaler,
1 realtime base and 1 input capture
– Two 12-bit Auto-reload Timers with 4 PWM
Device Summary
■
SO20
DIP20
QFN20
SO16
DIP16
300”
outputs, 1 input capture, 4 output compare
and one pulse functions
Communication Interface
– SPI synchronous serial interface
Interrupt Management
– 12 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (on 4 vectors)
Analog Comparator
A/D Converter
– 7 input channels
– Fixed gain Op-amp
– 13-bit precision for 0 to 430 mV (@ 5V V
DD
)
– 10-bit precision for 430 mV to 5V (@ 5V V
DD
)
Instruction Set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode de-
tection
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
Development Tools
– Full hardware/software development package
– DM (Debug Module)
ST7LITE15B
ST7LITE19B
■
■
■
■
■
■
Features
Program memory - bytes
RAM (stack) - bytes
Data EEPROM - bytes
Peripherals
Operating Supply
CPU Frequency
Operating Temperature
Packages
ST7LITE10B
2K/4K
256 (128)
-
-
128
Lite Timer with Wdg, Autoreload
Lite Timer with Wdg, Autoreload Timer with 32-MHz input clock, SPI,
Timer, SPI, 10-bit ADC with Op-Amp
10-bit ADC with Op-Amp, Analog Comparator
2.7V to 5.5V
Up to 8Mhz(w/ ext OSC at 16MHz)
Up to 8Mhz (w/ ext OSC at 16MHz or int 1MHz RC 1%, PLLx8/4MHz)
-40°C to +85°C / -40°C to +125°C
SO20 300”, DIP20, SO16 300”, DIP16
SO20 300”, DIP20, SO16 300”, DIP16, QFN20
Rev 6
June 2008
1/159
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
159
. 48
...
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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Table of Contents
10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.8 MULTIPLEXED INPUT/OUTPUT PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.2 DUAL 12-BIT AUTORELOAD TIMER 4 (AT4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.5 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.6 ANALOG COMPARATOR (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 137
13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
13.12 ANALOG COMPARATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
13.13 PROGRAMMABLE INTERNAL VOLTAGE REFERENCE CHARACTERISTICS . . . . . 143
13.14 CURRENT BIAS CHARACTERISTICS (FOR COMPARATOR AND INTERNAL VOLTAGE
REFERENCE) 143
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
14.2 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 149
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
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ST7LITE1xB
1 INTRODUCTION
The ST7LITE1xB is a member of the ST7 micro-
controller family. All ST7 devices are based on a
common industry-standard 8-bit core, featuring an
enhanced instruction set.
The ST7LITE1xB features FLASH memory with
byte-by-byte In-Circuit Programming (ICP) and In-
Application Programming (IAP) capability.
Under software control, the ST7LITE1xB device
can be placed in WAIT, SLOW, or HALT mode, re-
ducing power consumption when the application is
in idle or standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
Figure 1. General Block Diagram
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in
section 13 on page 110.
The ST7LITE1xB fea-
tures an on-chip Debug Module (DM) to support
In-Circuit Debugging (ICD). For a description of
the DM registers, refer to the ST7 ICC Protocol
Reference Manual.
Programmable
Internal Reference
Comparator
Int.
1% RC
1MHz
PLL
8MHz -> 32MHz
PLL x 8
or PLL X4
CLKIN
/2
OSC1
OSC2
Ext.
OSC
1MHz
to
16MHz
12-Bit
Auto-Reload
TIMER 2
8-Bit
LITE TIMER 2
Internal
CLOCK
PA7:0
(8 bits)
PB6:0
(7 bits)
PC1:0
(2 bits)
PORT A
PORT B
ADDRESS AND DATA BUS
LVD, AVD
V
DD
V
SS
RESET
POWER
SUPPLY
CONTROL
8-BIT CORE
ALU
PORT C
ADC
+ OpAmp
SPI
PROGRAM
MEMORY
(up to 4K Bytes)
Debug Module
RAM
(256 Bytes)
DATA EEPROM
(128 Bytes)
WATCHDOG
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1
ST7LITE1xB
2 PIN DESCRIPTION
Figure 2. 20-Pin SO and DIP Package Pinout
V
SS
V
DD
RESET
COMPIN+/SS/AIN0/PB0
SCK/AIN1/PB1
MISO/AIN2/PB2
MOSI/AIN3/PB3
COMPIN-/CLKIN/AIN4/PB4
AIN5/PB5
AIN6/PB6
1
2
3
4
5
6
7
8
9
10
ei2
ei1
ei3
ei0
20
19
18
17
16
15
14
13
12
11
OSC1/CLKIN/PC0
OSC2/PC1
PA0 (HS)/LTIC
PA1 (HS)/ATIC
PA2 (HS)/ATPWM0
PA3 (HS)/ATPWM1
PA4 (HS)/ATPWM2
PA5 (HS)/ATPWM3/ICCDATA
PA6/MCO/ICCCLK/BREAK
PA7(HS)/COMPOUT
(HS) 20mA High sink capability
eix associated external interrupt vector
Figure 3. 20-Pin QFN Package Pinout
PC0/OSC1/CLKIN
20 19 18
17
16
15
ei0
PC1/OSC2
V
DD
V
SS
RESET
COMPIN+/SS/AIN0/PB0
SCK/AIN1/PB1
MISO/AIN2/PB2
MOSI/AIN3/PB3
COMPIN-/CLKIN/AIN4/PB4
1
2
3
4
5
ei2
6
7
8
9
10
ei1
ei3
PA0 (HS)/LTIC
PA1 (HS)/ATIC
PA2 (HS)/ATPWM0
PA3 (HS)/ATPWM1
PA4 (HS)/ATPWM2
PA5 (HS)/ATPWM3/ICCDATA
14
13
12
11
COMPOUT/PA7(HS)
MCO/ICCCLKBREAK/PA6
AIN5/PB5
AIN6/PB6
(HS) 20mA High sink capability
eix associated external interrupt vector
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