STB130N6F7
N-channel 60 V, 4.2 mΩ typ., 80 A STripFET™ F7
Power MOSFET in a D²PAK package
Datasheet - production data
Features
Order code
V
DS
60 V
R
DS(on)
max.
5.0 mΩ
I
D
80 A
P
TOT
160 W
TAB
STB130N6F7
3
1
Among the lowest R
DS(on)
on the market
Excellent figure of merit (FoM)
Low C
rss
/C
iss
ratio for EMI immunity
High avalanche ruggedness
D2PAK
Applications
Switching applications
Figure 1: Internal schematic diagram
Description
This N-channel Power MOSFET utilizes
STripFET™ F7 technology with an enhanced
trench gate structure that results in very low on-
state resistance, while also reducing internal
capacitance and gate charge for faster and more
efficient switching.
D(2, TAB)
G(1)
S(3)
AM01475v1_
Tab
Table 1: Device summary
Order code
STB130N6F7
Marking
130N6F7
Package
D²PAK
Packing
Tape and reel
December 2015
DocID027380 Rev 5
1/14
www.st.com
This is information on a product in full production.
Contents
STB130N6F7
Contents
1
2
3
4
Electrical ratings ............................................................................. 3
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 5
Test circuits ..................................................................................... 7
Package information ....................................................................... 8
4.1
4.2
D²PAK (TO-263) type A package information ................................... 8
D²PAK packing information ............................................................. 11
5
Revision history ............................................................................ 13
2/14
DocID027380 Rev 5
STB130N6F7
Electrical ratings
1
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
V
DS
V
GS
I
D
(1)
I
DM
(2)
P
TOT
E
AS
(3)
T
stg
T
j
Notes:
(1)
(2)
(3)
Parameter
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
case
= 25 °C
Drain current (continuous) at T
case
= 100 °C
Drain current (pulsed)
Total dissipation at T
case
= 25 °C
Single pulse avalanche energy
Storage temperature
Operating junction temperature
Value
60
±20
80
80
320
160
200
-55 to 175
Unit
V
V
A
A
W
mJ
°C
Current is limited by package.
Pulse width is limited by safe operating area.
starting T
j
= 25 °C, I
D
= 20 A, V
DD
= 40 V.
Table 3: Thermal data
Symbol
R
thj-case
R
thj-amb
(1)
Notes:
(1)
Parameter
Thermal resistance junction-case
Thermal resistance junction-ambient
Value
0.94
35
Unit
°C/W
When mounted on a 1-inch² FR-4, 2 Oz copper board.
DocID027380 Rev 5
3/14
Electrical characteristics
STB130N6F7
2
Electrical characteristics
(T
case
= 25 °C unless otherwise specified)
Table 4: Static
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter
Drain-source breakdown voltage
Zero gate voltage drain current
Gate-body leakage current
Gate threshold voltage
Static drain-source on-resistance
Test conditions
V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 60 V
V
DS
= 0 V, V
GS
= 20 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 40 A
2
4.2
Min.
60
1
100
4
5.0
Typ.
Max.
Unit
V
µA
nA
V
mΩ
Table 5: Dynamic
Symbol
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
= 30 V, I
D
= 80 A,
V
GS
= 10 V (see
Figure
14: "Test circuit for gate
charge behavior")
Table 6: Switching times
Symbol
t
d(on)
t
r
t
d(off)
t
f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
V
DD
= 30 V, I
D
= 40 A,
R
G
= 4.7 Ω, V
GS
= 10 V (see
Figure 13: "Test circuit for
resistive load switching
times"
and
Figure 18:
"Switching time waveform")
Table 7: Source-drain diode
Symbol
V
SD
(1)
t
rr
Q
rr
I
RRM
Notes:
(1)
Test conditions
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0 V
Min.
-
-
-
-
-
-
Typ.
2600
1200
115
42
13.6
13
Max.
-
-
-
-
-
-
Unit
pF
nC
Min.
-
-
-
-
Typ.
24
44
62
24
Max.
-
-
-
-
Unit
ns
Parameter
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
V
GS
= 0 V, I
SD
= 80 A
I
SD
= 80 A, di/dt = 100 A/µs,
V
DD
= 48 V (see
Figure 15:
"Test circuit for inductive load
switching and diode recovery
times")
Min.
-
-
-
-
Typ.
Max.
1.2
Unit
V
ns
nC
A
50
56
2.2
Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
4/14
DocID027380 Rev 5
STB130N6F7
Electrical characteristics
2.1
Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
DocID027380 Rev 5
5/14
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