Gr
Pr
STB/P60L60A
Ver 3.0
S a mHop Microelectronics C orp.
N-Channel Logic Level Enhancement Mode Field Effect Transistor
PRODUCT SUMMARY
V
DSS
60V
I
D
65A
R
DS(ON)
(m
Ω
) Typ
15
@
VGS=10V
FEATURES
Super high dense cell design for extremely low RDS(ON).
High power and current handling capability.
TO-220 & TO-263 package.
D
D
G
S
G
D
S
G
S TP S E R IE S
TO-220
S TB S E R IE S
TO-263(DD-P AK)
S
ABSOLUTE MAXIMUM RATINGS (
T
C
=25
°
C unless otherwise noted
)
Symbol
V
DS
V
GS
I
D
I
DM
E
AS
P
D
T
J,
T
STG
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
-Pulsed
Avalanche Energy
d
b
a
Limit
60
±20
T
C
=25 °C
T
C
=70 °C
65
54
190
156
a
Units
V
V
A
A
A
mJ
W
W
°C
Maximum Power Dissipation
T
C
=25°C
T
C
=70°C
125
87.5
-55 to 175
Operating Junction and Storage
Temperature Range
THERMAL CHARACTERISTICS
R
JC
Thermal Resistance, Junction-to-Case
R
JA
Thermal Resistance, Junction-to-Ambient
1.2
62.5
°C/W
°C/W
Details are subject to change without notice.
Oct,13,2011
1
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STB/P60L60A
Ver 3.0
ELECTRICAL CHARACTERISTICS
(
T
C
=25
°
C unless otherwise noted
)
4
Symbol
Parameter
Conditions
V
GS
=0V , I
D
=250uA
V
DS
=48V , V
GS
=0V
Min
60
Typ
Max
Units
V
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
BV
DSS
Zero Gate Voltage Drain Current
I
DSS
I
GSS
Gate-Body leakage current
ON CHARACTERISTICS
V
GS(th)
Gate Threshold Voltage
R
DS(ON)
g
FS
DYNAMIC
C
ISS
C
OSS
C
RSS
Drain-Source On-State Resistance
Forward Transconductance
CHARACTERISTICS
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
b
V
GS
= ±20V , V
DS
=0V
1
±100
uA
nA
V
DS
=V
GS
, I
D
=250uA
V
GS
=10V , I
D
=32.5A
V
DS
=20V , I
D
=32.5A
2
2.8
15
48
4
19
V
m ohm
S
V
DS
=25V,V
GS
=0V
f=1.0MHz
2300
142
108
pF
pF
pF
SWITCHING CHARACTERISTICS
t
D(ON)
Turn-On DelayTime
tr
Rise Time
t
D(OFF)
Turn-Off DelayTime
tf
Fall Time
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
=30V
I
D
=1A
V
GS
=10V
R
GEN
=60 ohm
V
DS
=30V,I
D
=25A,V
GS
=10V
V
DS
=30V,I
D
=25A,
V
GS
=10V
63
71
162
42
28
5
11
ns
ns
ns
ns
nC
nC
nC
DRAIN-SOURCE DIODE CHARACTERISTICS
V
SD
Diode Forward Voltage
V
GS
=0V,I
S
=1A
0.75
1.3
V
Notes
_
a.Surface Mounted on FR4 Board,t < 10sec.
_
_
b.Pulse Test:Pulse Width < 300us, Duty Cycle < 2%.
c.Guaranteed by design, not subject to production testing.
d.Starting T
J
=25
°
C,L=0.5mH,V
DD
= 30V.(See Figure13)
Oct,13,2011
2
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STB/P60L60A
Ver 3.0
100
65
V
GS
= 10V
I
D
, Drain Current(A)
V
GS
= 8V
V
GS
= 7V
V
GS
= 6V
I
D
, Drain Current(A)
80
52
60
39
Tj=125 C
40
26
25 C
13
-55 C
20
0
0
0.5
1.0
1.5
2.0
V
GS
= 5V
0
2.5
3.0
0
1.5
3.0
4.5
6.0
7.5
9.0
V
DS
, Drain-to-Source Voltage(V)
V
GS
, Gate-to-Source Voltage(V)
Figure 1. Output Characteristics
60
50
40
30
20
10
1
V
G S
=10V
Figure 2. Transfer Characteristics
2.0
1.8
1.6
1.4
1.2
1.0
0.8
V
G S
=10V
I
D
=32.5A
R
DS(on)
, On-Resistance
Normalized
R
DS(on)
(m
Ω
)
1
20
40
60
80
100
0
25
50
75
100
125
I
D
, Drain Current(A)
Tj, Junction Temperature(° C )
150
T j (
°C )
Figure 3. On-Resistance vs. Drain Current
and Gate Voltage
1.6
Figure 4. On-Resistance Variation with Drain
Current and Temperature
BVDSS, Normalized
Drain-Source Breakdown Voltage
1.4
Vth, Normalized
Gate-Source Threshold Voltage
1.4
1.2
1.0
0.8
0.6
0.4
0.2
-50
-25
0
25
50
75
V
DS
=V
G S
I
D
=250uA
I
D
=250uA
1.3
1.2
1.1
1.0
0.9
0.8
-50
100 125 150
-25
0
25
50
75
100 125 150
Tj, Junction Temperature(° C )
Tj, Junction Temperature(° C )
Figure 5. Gate Threshold Variation
with Temperature
Figure 6. Breakdown Voltage Variation
with Temperature
Oct,13,2011
3
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STB/P60L60A
Ver 3.0
90
60
I
D
= 32.5A
75
R
DS(on)
(m
Ω
)
60
45
125 C
30
75 C
15
0
25 C
0
2
4
6
8
10
Is, Source-drain current(A)
125 C
10
25 C
75 C
1
0
0.3
0.6
0.9
1.2
1.5
V
GS
, Gate-to-Source Voltage(V)
V
SD
, Body Diode Forward Voltage(V)
Figure 7. On-Resistance vs.
Gate-Source Voltage
3000
Figure 8. Body Diode Forward Voltage
Variation with Source Current
10
V
GS
, Gate to Source Voltage(V)
2500
8
C, Capacitance(pF)
Ciss
2000
1500
1000
500
0
0
Crss
5
10
15
20
25
30
V
DS
=30V
I
D
=25A
6
4
2
Coss
0
0
4
8
12
16
20
24
28
32
V
DS
, Drain-to-Source Voltage(V)
Qg, Total Gate Charge(nC)
Figure 9. Capacitance
Figure 10. Gate Charge
300
100
TD(off )
I
D
, Drain Current(A)
100
R
(O
DS
Switching Time(ns)
TD(on)
Tr
L
N)
im
it
1m
s
10
0u
s
Tf
10
m
DC
s
10
10
V
DS
=30V,I
D
=1A
V
GS
=10V
1
1
10
100
1
0.3
0.1
V
GS
=10V
Single Pulse
T
C
=25 C
1
10
60
Rg, Gate Resistance(
Ω
)
V
DS
, Drain-Source Voltage(V)
Figure 11. switching characteristics
Figure 12. Maximum Safe Operating Area
Oct,13,2011
4
www.samhop.com.tw
STB/P60L60A
Ver 3.0
V
( BR )D S S
tp
L
V
DS
RG
20V
D .U .T
I
A S
tp
+
-
V
DD
0.0 1
I
AS
Unclamped Inductive Waveforms
Figure 13b.
Unclamped Inductive Test Circuit
Figure 13a.
2
r(t),Normalized Effective
Transient Thermal Impedance
1
D=0.5
0.2
0.1
0.1
0.05
0.02
0.01
S ingle P uls e
P
DM
t
1
t
2
1.
2.
3.
4.
R
J C
(t)=r (t) * R
J C
R
J C
=S ee Datas heet
T
J M-
T
C
= P * R
J C
(t )
Duty C ycle, D=t1/t2
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
Square Wave Pulse Duration (msec)
Figure 14. Normalized Thermal Transient Impedance Curve
Oct,13,2011
5
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PCB设计
