STB70NF3LL
N-channel 30V - 0.0075Ω - 70A - D
2
PAK
Low gate charge STripFET™ II Power MOSFET
General features
Type
STB70NF3LL
■
■
■
V
DSS
30V
R
DS(on)
< 0.0095Ω
I
D
70A
Optimal R
DS(on)
x Qg trade-off @ 4.5V
Conduction losses reduced
Switching losses reduced
3
1
D²PAK
Description
This application specific Power MOSFET is the
third genaration of STMicroelectronis unique
"Single Feature Size™" strip-based process. The
resulting transistor shows the best trade-off
between on-resistance and gate charge. When
used as high and low side in buck regulators, it
gives the best performance in terms of both
conduction and switching losses. This is
extremely important for motherboards where fast
switching and high efficiency are of paramount
importance.
Internal schematic diagram
Applications
■
Switching application
Order codes
Part number
STB70NF3LLT4
Marking
B70NF3LL@
Package
D
2
PAK
Packaging
Tape & reel
July 2006
Rev 7
1/13
www.st.com
13
Contents
STB70NF3LL
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
4
5
6
Test circuit
................................................ 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
STB70NF3LL
Electrical ratings
1
Electrical ratings
Table 1.
Symbol
V
DS
V
DGR
V
GS
I
D(1)
I
D
I
DM(2)
P
TOT
dv/dt
(3)
E
AS (4)
T
stg
T
J
Absolute maximum ratings
Parameter
Drain-source voltage (V
GS
= 0)
Drain-gate voltage (R
GS
= 20 kΩ)
Gate- source voltage
Drain current (continuous) at T
C
= 25°C
Drain current (continuous) at T
C
= 100°C
Drain current (pulsed)
Total dissipation at T
C
= 25°C
Derating factor
Peak diode recovery voltage slope
Single pulse avalanche energy
Storage temperature
-55 to 175
Operating junction temperature
°C
Value
30
30
± 16
70
50
280
100
0.67
5.5
500
Unit
V
V
V
A
A
A
W
W/°C
V/ns
mJ
1. Current limited by the package
2. Pulse width limited by safe operating area
3.
4.
I
SD
≤
70A, di/dt
≤
350A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
T
JMAX
Starting T
J
= 25
o
C, I
D
= 35A, V
DD
= 25V
Table 2.
Symbol
R
thJC
R
thJA
T
l
Thermal data
Parameter
Thermal resistance junction-case Max
Thermal resistance junction-ambient Max
Maximum lead temperature for soldering
purpose
Value
1.5
62.5
300
Unit
°C/W
°C/W
°C
3/13
Electrical characteristics
STB70NF3LL
2
Electrical characteristics
(T
CASE
=25°C unless otherwise specified)
Table 3.
Symbol
V
(BR)DSS
On/off states
Parameter
Drain-source
Breakdown voltage
Zero gate voltage
Drain current (V
GS
= 0)
Gate-body leakage
Current (V
DS
= 0)
Gate threshold voltage
Static drain-source on
resistance
Test conditions
I
D
= 250 µA, V
GS
= 0
V
DS
= Max rating
V
DS
= Max rating
T
C
= 125°C
V
GS
= ± 16 V
V
DS
= V
GS
V
GS
= 10V
V
GS
= 4.5V
I
D
= 250µA
I
D
= 35A
I
D
= 18A
1
0.0075 0.0095
0.010 0.012
Min
30
1
10
±100
Typ
Max
Unit
V
µA
µA
nA
V
Ω
Ω
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Table 4.
Symbol
g
fs
C
iss
C
oss
C
rss
Dynamic
Parameter
Forward
Transconductance
Input capacitance
Output capacitance
Reverse transfer
capacitance
Test conditions
V
DS
= 15V
I
D
= 35A
Min
Typ
25
1650
540
130
Max
Unit
S
pF
pF
pF
V
DS
= 25V f = 1MHz V
GS
= 0
4/13
STB70NF3LL
Electrical characteristics
Table 5.
Symbol
t
d(on)
t
r
Q
g
Q
gs
Q
gd
t
d(off)
t
f
Switching times
Parameter
Turn-on delay time
Rise time
Total gate charge
Gate-source charge
Gate-drain charge
Turn-off delay time
Fall time
Test conditions
I
D
= 35A
V
DD
= 15V
V
GS
= 4.5V
R
G
= 4.7Ω
(Resistive Load
Figure 16)
V
DD
= 15V I
D
= 70A
V
GS
= 4.5V
V
DD
= 15 V
I
D
= 35 A
V
GS
= 4.5 V
R
G
= 4.7Ω,
(Resistive Load
Figure 16)
Min
Typ
23
165
24
8.5
12
27
28
33
Max
Unit
ns
ns
nC
nC
nC
ns
ns
Table 6.
Symbol
I
SD
I
SDM
Source drain diode
Parameter
Source-drain current
Source-drain current
(pulsed)
Forward on voltage
I
SD
= 70 A
V
GS
= 0
42
52
2.5
Test conditions
Min
Typ
Max
70
280
1.3
Unit
A
A
V
ns
nC
A
(1)
V
SD (2)
t
rr
Q
rr
I
RRM
Reverse recovery time
I
SD
= 70 A di/dt = 100A/µs
T
J
= 150°C
Reverse recovery charge V
DD
= 20 V
Reverse recovery current (see test circuit
Figure 14)
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
5/13
