STEL-1377Q/S
Data Sheet
STEL-1377Q
(Quadrature)
STEL-1377S
(Single Channel)
32-Bit Resolution FM & PM
Modulated Direct Digital
Frequency Synthesizer
R
FEATURES
s
HIGH MAXIMUM CLOCK FREQUENCY
s
s
s
s
- UP TO 60 MHz
HIGH OUTPUT BANDWIDTH
- UP TO 25 MHz OUTPUT FREQUENCY
HIGH FREQUENCY–RESOLUTION
- 32 BITS, 14 milliHz @ 60 MHz
HIGH SPEED FREQUENCY HOPPING
OR MODULATION
- MAXIMUM UPDATE RATE 15 MHz
PRECISION PHASE MODULATION
- 12 BITS, 0.09° RESOLUTION
CAN BE USED FOR LINEAR PM OR
PULSE-SHAPED PSK AT UP TO 15 MHz
PRECISION FREQUENCY MODULATION
- 16 BITS RESOLUTION, CAN BE USED
FOR LINEAR FM OR PULSE-SHAPED FSK
SINE AND COSINE OUTPUTS
(STEL-1377Q) OR SINGLE ENDED
OUTPUT (STEL-1377S) FOR LOWER
POWER CONSUMPTION
HIGH-SPEED, LOW GLITCH ECL DACS
s
s
s
s
HIGH SPECTRAL PURITY
The STEL-1377Q is a complete Quadrature Direct
Digital Frequency Synthesizer (DDS) in a single DIL
package measuring only 3.75 x 1.6". The STEL-1377S
provides a single ended output only. The STEL-1377
makes it possible to use DDS technology in
applications requiring quadrature outputs as well as
frequency and phase modulation in a small package.
The STEL-1377 is a printed circuit unit using the STEL-
1177 PM and FM Numerically Controlled Oscillator
(NCO) chip driving two high-speed 10-bit DACs
(Sony CX20201A-1) to generate quadrature analog
output signals. Surface mount technology (SMT)
components are used throughout. The device is
guaranteed to operate at clock frequencies up to 60
MHz over the temperature range of 0-70°C, giving an
output frequency range of 0 to over 25 MHz, with a
frequency resolution of 14 milliHz at a clock frequency
of 60 MHz. In addition, the device features phase and
frequency modulation capabilities at extremely high
modulation rates, up to 25% of the clock frequency. For
more detailed information on the STEL-1177 NCO
please refer to the STEL-1177 data sheet. For more
information on the DAC please refer to the Sony
CX20201A-1 data sheet. The output frequency is
directly related to the clock frequency by the
following:
f
o
=
where:
and:
f
c
x
∆
-Phase
2
32
- –65 dBc SPURIOUS TYPICAL
s
3.75" BY 1.6" BY 0.4"
BLOCK DIAGRAM
DATA
ADDR
WRSTB
FRLD
FRSEL
PHLD
PHSEL
RESET
FMOD
FMAD
RATE
SIMLD
FMSUB
FMLD
16
2
2
STEL-
1177
NCO
10
8
4
f
o
is the frequency of the output signal
f
c
is the clock frequency.
FMSYNC
10
CMOS-ECL 10
TRANS-
LATORS
SIN
10-BIT
DAC
OUT
CMOS-ECL 10
TRANS-
LATORS
COS
10-BIT
DAC
OUT
(STEL-
1377Q
ONLY)
CLOCK
ECL/CMOS LEVEL SHIFTER
VREF
STEL-1377Q/S
2
PIN CONFIGURATION
Package: 63-pin DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
0.4" max.
0.2" max.
Pin diameter: 0.018" ± .002"
0.1" ± .005"
C omp onent area, unencap sulated
3.75" ± .01"
1.5" ± .01"
1.6" ± .01"
PIN CONNECTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLOCK
V
EE
RATE
0
RATE
1
FMLD
FMSUB
FMADDR
0
FMADDR
1
FMOD
0
FMOD
1
FMOD
2
FMOD
3
FMOD
4
FMOD
5
FMOD
6
FMOD
7
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
FMOD
8
FMOD
9
FMOD
10
FMOD
11
FMOD
12
FMOD
13
FMOD
14
FMOD
15
SIMLD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DATA
7
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DATA
6
DATA
5
DATA
4
DATA
3
DATA
2
DATA
1
DATA
0
ADDR
0
ADDR
1
ADDR
2
ADDR
3
FRSEL
FMSYNC
V
SS
FRLD
RESET
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
PHLD
WRSTB
PHSEL
V
DD
CSEL
V
SS
CIN
V
DD
DV
EE (DAC)
AV
EE (DAC)
V
SS
OUT (SIN)
V
EE
V
REF
OUT (COS)
(STEL-1377Q only)
3
STEL-1377Q/S
CIRCUIT DESCRIPTION
The frequency of the NCO is determined by the
number stored in the
∆-Phase
register which is
programmed from the interface bus. The number
stored in the
∆-Phase
register is added to the current
contents of the accumulator every clock cycle to
generate a monotonically increasing phase angle. By
modulating this number the frequency of the NCO can
be modulated. The NCO generates digitized sine and
cosine functions by addressing sine and cosine lookup
tables with the phase accumulator. Phase modulation
data is added to the accumulator output before the
lookup tables. Please refer to the STEL-1177 data sheet
for information on programming the NCO.
The NCO output is passed through CMOS to ECL level
translators and loaded synchronously into two high-
speed 10-bit DACs. The full-scale outputs of the DACs
is determined by the voltage on the VREF input, and
this can be used to amplitude modulate the output
signals.
corresponding to zero phase until new frequency or
modulation (either frequency or phase) data is loaded
with the
FRLD, FMLD,
or
PHLD
inputs after the
RESET
returns high.
CLOCK
All synchronous functions performed within the NCO
are referenced to the rising edge of the
CLOCK
input.
The
CLOCK
signal should be a square wave or sine
wave at a maximum frequency of 60 MHz. A non-
repetitive
CLOCK
waveform is permissible as long as
the minimum duration positive or negative pulse on
the waveform is always greater than 5 nanoseconds.
CSEL
The
Chip Select
input is used to control the writing of
data into the chip. It is active low. When this input is
high all data writing via the
DATA
7-0
bus is inhibited.
DATA
7
through DATA
0
The 8-bit
DATA
7-0
bus is used to program the two 32-
bit
∆-Phase
Registers and the two 12-bit Phase
Modulation Registers.
DATA
0
is the least significant
bit of the bus. The data programmed into the
∆-Phase
registers in this way determines the carrier frequency
of the NCO.
ADDR
3
through ADDR
0
The four address lines
ADDR
3-0
control the use of the
DATA
7-0
bus for writing frequency data to the
∆-Phase
Buffer Registers, and phase data to the Phase Buffer
Registers, as shown in the table:
ADDR
3
ADDR
1
ADDR
0
Register Field
0
CLOCK GENERATION BLOCK
The clock generation block generates the different
clocks required for the NCO and DAC blocks from the
incoming ECL or sinusoidal clock signal.
DAC BLOCK
The DAC block consists of the Sony CX20201A-1
digital to analog converters and the necessary
supporting circuitry.
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
∆-Phase
Bits 0 (LSB)–7
∆-Phase
Bits 8–15
∆-Phase
Bits 16–23
∆-Phase
Bits 24–31
Sine Bits 0(LSB)–3*
Sine Bits 4-11*
Cosine Bits 0(LSB)–3*
Cosine Bits 4-11*
FUNCTION BLOCK DESCRIPTION
NCO BLOCK
The NCO block is the core of the STEL-1377 DDS. It
consists of a front-end which may be programmed
from the control inputs. The NCO is described fully in
the STEL-1177 data sheet. Please refer to this data sheet
for more detailed information.
LEVEL TRANSLATOR BLOCK
The outputs of the NCO block are CMOS level digital
signals. These are translated to ECL levels for
optimum operation of the DAC.
INPUT SIGNALS
RESET
The
RESET
input is asynchronous and active low, and
clears all the registers in the device. When
RESET
goes
low, all registers are cleared within 20 nsecs, and
normal operation will resume after this signal returns
high. The outputs will go to the zero level during the
reset, and thereafter will remain at the value
ADDR
3
ADDR
2
0
0
1
0
1
X
Register Selected
∆-Phase
Buffer Register 'A'
∆-Phase
Buffer Register 'B'
Phase Buffer Registers
Note: The Phase Buffer Registers are 12-bit registers.
When the least significant bytes of these registers are
selected (ADDR
3-0
=1XX0),
DATA
7-4
is written into
STEL-1377Q/S
4
Bits 3–0 of the registers. In all cases, it is not necessary
to reload unchanged bytes, and the byte loading
sequence may be random.
WRSTB
The
Write Strobe
input is used to latch the data on the
DATA
7-0
bus into the device. On the rising edge of the
WRSTB
input, the information on the 8-bit data bus is
transferred to the buffer register selected by the
ADDR
3-0
bus.
FRSEL
The
Frequency Register Select
line is used to control
the mux which selects the
∆-Phase
Buffer Register in
use. When this signal is high
∆-Phase
Buffer Register
'A' is selected as the source for the
∆-Phase
ALU, and
the frequency corresponding to the data stored in this
register will be generated by the NCO after the next
falling edge on the
FRLD
input. When this line is low,
∆-Phase
Buffer Register 'B' is selected as the source.
FRLD
The
Frequency Load
input is used to control the
transfer of the data from the
∆-Phase
Buffer Registers
to the
∆-Phase
ALU. The data at the output of the Mux
Block must be valid during the clock cycle following
the falling edge of
FRLD.
The data is then transferred
during the subsequent cycle. The frequency of the
NCO output will change 19 clock cycles after the
FRLD
command due to pipelining delays.
PHSEL
The
Phase
Source
Select
input selects the sources of
data for the Phase ALUs. When it is high the sources
are the Sine and Cosine Phase Buffer Registers. They
are loaded from the
DATA
7-0
bus by setting address
line
ADDR
3
high, as shown in the tables. When
PHSEL
is low, the sources for the phase modulation
data are the
DATA
7-0
and
ADDR
3-0
inputs, and the
data will be loaded independently of the states of
WRSTB
and
CSEL.
The data on these 12 lines is
presented directly as a parallel 12-bit word to both
Phase ALUs, allowing high-speed phase modulation.
The 12-bit value is latched into the Phase ALUs by
means of the
PHLD
input. The data on the
ADDR
3-0
lines is mapped onto Phase Bits 3 to 0 and the data on
the
DATA
7-0
lines are mapped onto Phase Bits 11 to 4
in this case. When using the parallel phase load mode
CSEL
and/or
WRSTB
should remain high to ensure
that the phase data is not written into the phase and
frequency buffer registers of the STEL-1377.
PHLD
The
Phase Load
input is used to control the latching of
the Phase Modulation data into the Phase ALUs. The
12-bit data at the output of the Phase Modulation
Control Block must be valid during the clock cycle
following the falling edge of
PHLD.
The data is then
transferred during the subsequent cycle. The 12-bit
phase data is added to the 12 most significant bits of the
accumulator output, so that the MSB of the phase data
represents a 180° phase change. The source of this data
will be determined by the state of
PHSEL.
The phase
of the NCO output will change 12 clock cycles after the
PHLD
command, due to pipelining delays.
FMOD
15
through FMOD
0
The
Frequency Modulation
bus is a 16-bit bus on
which the FM data is loaded into the STEL-1177. The
data should be a 16-bit unsigned number.
FMSUB
The
FM Subtract
input controls the Add/Subtract
operation of the
∆-Phase
ALU. When it is high the FM
data on the
FMOD
15-0
bus will be subtracted from the
carrier frequency, and when it is low the FM data will
be added to the carrier frequency. In this way the FM
data can be treated as a 17-bit signed-magnitude
number, where the
FMSUB
signal is the sign bit.
FMADDR
1
through FMADDR
0
The two inputs
FMADDR
1-0
set the deviation of the
frequency modulation by controlling the significance
of the FM data in relation to the carrier frequency data.
The FM data word will be multiplied by 2
0
, 2
4
, 2
8
, or 2
12
according to the state of
FMADDR
1-0
, and the
consequent resolution and maximum values of the
deviation are shown in the table below. The deviations
and resolutions shown are for a clock frequency of 60
MHz.
FM-
FM-
Mult. factor Maximum
ADDR
1
ADDR
0
of FM data deviation
0
0
1
1
0
1
0
1
2
0
2
4
2
8
2
12
±
915 Hz
±
234 KHz
Resol-
ution
14 mHz
3.6 Hz
±
14.6 KHz 0.22 Hz
±
3.75 MHz 57 Hz
FMLD
The
FM Load
input controls the writing of the
frequency modulation data on the
FMOD
15-0
bus and
the
FMSUB
input into the device. When
RATE
1-0
=
00
the data at the output of the Frequency Modulation
Control Block must be valid during the clock cycle
following the falling edge of
FMLD.
The data is then
transferred during the subsequent cycle. When
RATE
1-0
=
01, 10 or 11 are selected the FM data will be
loaded automatically without the use of the
FMLD
input. Note that
FMLD
must be held low during
automatic operation, otherwise the loading will be
inhibited.
5
STEL-1377Q/S
