STF12NK65Z
N-channel 650 V, 0.57
Ω
10 A, TO-220FP
,
Zener-protected SuperMESH™ Power MOSFET
Features
Order code
STF12NK65Z
V
DSS
650 V
R
DS(on)
max.
< 0.7
Ω
I
D
10 A
P
W
35 W
■
■
■
■
■
Extremely high dv/dt capability
100% avalanche tested
Gate charge minimized
Very low intrinsic capacitance
Very good manufacturing repeatability
Application
Switching applications
Description
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O
This N-channel SuperMESH™ Power MOSFET is
obtained through an extreme optimization of ST’s
well established strip-based PowerMESH™
layout. In addition to pushing on-resistance
significantly down, special care is taken to ensure
a very good dv/dt capability for the most
demanding applications. Such series
complements ST full range of high voltage Power
MOSFETs including revolutionary MDmesh™
products.
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Figure 1.
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TO-220FP
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1
2
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Internal schematic diagram
D(2)
G(1)
S(3)
AM01476v1
Table 1.
Device summary
Marking
12NK65Z
Package
TO-220FP
Packaging
Tube
Order code
STF12NK65Z
October 2010
Doc ID 18060 Rev 1
1/12
www.st.com
12
Contents
STF12NK65Z
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
4
5
Test circuits
............................................... 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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2/12
Doc ID 18060 Rev 1
STF12NK65Z
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
V
DS
V
GS
I
D
I
D
I
DM (1)
P
TOT
Absolute maximum ratings
Parameter
Drain-source voltage (V
GS
= 0)
Gate- source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Derating factor
Value
650
± 30
10
6.3
40
35
1.2
Unit
V
V
A
A
V
ISO
dv/dt
(2)
T
stg
T
j
Insulation withstand voltage (RMS) from all
three leads to external heat sink
(t = 1 s; T
C
= 25 °C)
Peak diode recovery voltage slope
Storage temperature
Max operating junction temperature
1. Pulse width limited by safe operating area
2. I
SD
≤
10 A, di/dt
≤
200 A/µs, V
DD
≤
V
(BR)DSS
, T
j
≤
T
JMAX.
Table 3.
Symbol
R
thj-case
R
thj-amb
Thermal data
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P
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T
l
Thermal resistance junction-case max
Thermal resistance junction-ambient max
Maximum lead temperature for soldering
purpose
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(s
t
b
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te
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ro
P
2500
4.5
- 55 to 150
150
uc
d
s)
t(
W
V
V/ns
°C
°C
A
W/°C
Parameter
Value
3.6
62.5
300
Unit
°C/W
°C/W
°C
Table 4.
Symbol
I
AR
E
AS
Avalanche characteristics
Parameter
Avalanche current, repetitive or not-repetitive
(pulse width limited by Tj Max)
Single pulse avalanche energy
(starting T
J
=25 °C, I
D
=I
AR
, V
DD
=50 V)
Value
10
225
Unit
A
mJ
Doc ID 18060 Rev 1
3/12
Electrical characteristics
STF12NK65Z
2
Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Table 5.
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
On/off states
Parameter
Drain-source
breakdown voltage
Zero gate voltage
drain current (V
GS
= 0)
Gate-body leakage
current (V
DS
= 0)
Gate threshold voltage
Static drain-source on
resistance
Test conditions
I
D
=1 mA, V
GS
= 0
V
DS
= max rating
V
DS
= max rating, T
C
= 125°C
V
GS
= ± 20 V
V
DS
= V
GS
, I
D
= 100 µA
V
GS
= 10 V, I
D
=10 A
Min.
650
1
50
Typ.
Max.
Unit
V
µA
µA
Table 6.
Symbol
g
fs (1)
C
iss
C
oss
C
rss
C
oss eq. (2)
Dynamic
Parameter
Forward transconductance
Input capacitance
V
DS
= 25 V, f = 1 MHz,
Output capacitance
V =0
Reverse transfer capacitance
GS
Equivalent output
capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Total gate charge
Gate-source charge
Gate-drain charge
Intrinsic gate resistance
b
O
et
l
so
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
R
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Min.
-
-
3
uc
d
3.75
0.57
Typ.
9.5
1837
208
48.8
122
25
14
55
11.5
62.6
9.6
36
1
± 10
4.5
0.7
s)
t(
µA
V
Ω
Test conditions
Max.
-
-
Unit
S
pF
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
Ω
V
DS
= 15 V, I
D
= 5 A
V
DS
=0, V
DS
= 0 to 520 V
V
DD
= 325 V, I
D
= 5 A,
R
G
= 4.7
Ω,
V
GS
= 10 V
(see
Figure 14)
V
DD
= 520 V, I
D
= 10 A,
V
GS
= 10 V
(see
Figure 15)
f = 1 MHz open drain
-
-
-
-
-
-
-
-
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
.
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Doc ID 18060 Rev 1
STF12NK65Z
Electrical characteristics
Table 7.
Symbol
I
SD
I
SDM(1)
V
SD(2)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Source drain diode
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 10 A, V
GS
= 0
I
SD
= 10 A,
di/dt = 100 A/µs
V
DD
= 60 V
(see
Figure 16)
I
SD
= 10 A,
di/dt = 100 A/µs
V
DD
= 60 V, Tj = 150 °C
(see
Figure 16)
-
-
Test conditions
Min.
-
-
436
3.4
15.4
Typ.
Max.
10
38
1.6
Unit
A
A
V
ns
µC
A
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. Pulse width limited by safe operating area
Table 8.
Symbol
Gate-source Zener diode
Parameter
BV
GSO(1)
Gate-source breakdown voltage
1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
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Min.
30
uc
d
Typ.
-
518
4.1
15.9
s)
t(
ns
µC
A
Test conditions
Max.
Unit
V
Igs=± 1mA (open drain)
Doc ID 18060 Rev 1
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