Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
−55
to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72199
S-60673Rev. B, 01-May-06
www.vishay.com
1
SPICE Device Model SUM40N02-12P
Vishay Siliconix
SPECIFICATIONS (T
J
= 25°C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
On-State Drain Current
a
a
Symbol
Test Condition
Simulated
Data
1.9
370
0.0093
0.012
0.019
0.91
Measured
Data
Unit
V
GS(th)
I
D(on)
V
DS
= V
GS
, I
D
= 250
µA
V
DS
= 5 V, V
GS
= 10 V
V
GS
= 10 V, I
D
= 20 A
V
A
0.0095
Ω
0.021
1.1
V
Drain-Source On-State Resistance
r
DS(on)
V
GS
= 10 V, I
D
= 20 A, T
J
= 125°C
V
GS
= 4.5 V, I
D
= 15 A
Forward Voltage
a
V
SD
I
F
= 40 A, V
GS
= 0 V
Dynamic
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
c
Gate-Source Charge
Gate-Drain Charge
c
Turn-On Delay Time
Rise Time
c
c
c
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
t
rr
I
F
= 40 A, di/dt = 100 A/µs
V
DD
= 10 V, R
L
= 0.25
Ω
I
D
≅
40 A, V
GEN
= 10 V, R
G
= 2.5
Ω
V
DS
= 10 V, V
GS
= 4.5 V, I
D
= 40 A
V
GS
= 0 V, V
DS
= 10 V, f = 1 MHz
973
358
179
7
3.5
2.6
10
9
24
10
15
1000
370
180
7.5
3.5
2.6
11
10
24
9
20
ns
nC
pF
Turn-Off Delay Time
c
Fall Time
c
Source-Drain Reverse Recovery Time
Notes
a. Pulse test; pulse width
≤
300
µs,
duty cycle
≤
2%.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
www.vishay.com
2
Document Number: 72199
S-60673Rev. B, 01-May-06
SPICE Device Model SUM40N02-12P
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25°C UNLESS OTHERWISE NOTED)
Document Number: 72199
S-60673Rev. B, 01-May-06
www.vishay.com
3
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