The SY10/100E151 offer 6 edge-triggered, high-speed,
master-slave D-type flip-flops with differential outputs,
designed for use in new, high-performance ECL systems.
The two external clock signals (CLK
1
, CLK
2
) are gated
through a logical OR operation before use as clocking
control for the flip-flops. Data is clocked into the flip-flops
on the rising edge of either CLK
1
or CLK
2
(or both). When
both CLK
1
and CLK
2
are at a logic LOW, data enters the
master and is transferred to the slave when either CLK
1
or
CLK
2
(or both) go HIGH.
The MR (Master Reset) signal operates asynchronously
to make all Q outputs go to a logic LOW.
BLOCK DIAGRAM
D
0
Q
0
R
D
1
D
R
D
2
D
R
D
3
D
R
D
4
D
R
D
5
D
R
CLK
1
CLK
2
M
R
Q
0
PIN CONFIGURATION
MR
CLK
2
CLK
1
NC
V
CCO
Q
5
Q
5
18
17
D
25 24 23 22 21 20 19
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
D
5
D
4
D
3
V
EE
D
2
D
1
D
0
26
27
28
1
2
3
4
5
6
7
8
9
10 11
Q
4
Q
4
V
CC
Q
3
Q
3
Q
2
Q
2
PLCC
TOP VIEW
J28-1
16
15
14
13
12
V
CCO
Q
0
Q
1
Q
1
Q
4
Q
4
Q
5
Q
5
PIN NAMES
Pin
D
0
–D
5
CLK
1
, CLK
2
MR
Q
0
–Q
5
Q
0
–Q
5
V
CCO
Function
Data Inputs
Clock Inputs
Master Reset
True Outputs
Inverting Outputs
V
CC
to Output
V
CCO
Rev.: E
NC
Q
0
Amendment: /0
1
Issue Date: November 2002
Micrel
SY10E151
SY100E151
TRUTH TABLES
(1)
Asynchronous Operation
Inputs
D
n
X
CLK
1
X
CLK
2
X
MR
H
Output
Q
n
(t + 1)
L
D
n
L
H
L
H
X
X
X
Synchronous Operation
Inputs
CLK
1
u
u
L
L
H
u
L
CLK
2
L
L
u
u
u
H
L
MR
L
L
L
L
L
L
L
Output
Q
n
(t + 1)
L
H
L
H
Q
n
(t)
Q
n
(t)
Q
n
(t)
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
t = Time before positive CLK transition
t+1 = Time after positive CLK transition
u = LOW-to-HIGH transition
DC ELECTRICAL CHARACTERISTICS
(1)
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
°
C
Symbol
I
IH
I
EE
Parameter
Input HIGH Current
Power Supply Current
10E
100E
NOTE:
1. Specification for packaged product only.
T
A
= +25
°
C
150
78
78
—
—
—
—
65
65
150
78
78
T
A
= +85
°
C
Max.
150
78
90
Unit
µA
mA
Condition
—
—
—
—
—
—
65
75
Min. Typ. Max. Min. Typ.
—
—
—
—
65
65
Max. Min. Typ.
2
Micrel
SY10E151
SY100E151
AC ELECTRICAL CHARACTERISTICS
(2)
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
°
C
Symbol
f
MAX
t
PLH
t
PHL
t
S
t
H
t
RR
t
PW
t
skew
t
r
t
f
Parameter
Max. Toggle Frequency
Propagation Delay to Output
CLK
MR
Set-up Time, D
Hold Time, D
Reset Recovery Time
Minimum Pulse Width
CLK, MR
Within-Device Skew
Rise/Fall Time
20% to 80%
1100 1400
475
475
0
350
750
400
—
300
650
650
–175
175
550
—
65
450
—
800
850
—
—
—
—
—
700
T
A
= +25
°
C
1100 1400
475
475
0
350
750
400
—
300
650
650
–175
175
550
—
65
450
—
800
850
—
—
—
—
—
700
T
A
= +85
°
C
Max.
—
800
850
—
—
—
—
—
700
ps
ps
ps
ps
ps
ps
—
—
—
—
1
—
Unit
MHz
ps
475
475
0
350
750
400
—
300
650
650
–175
175
550
—
65
450
Condition
—
—
1100 1400
Min. Typ. Max. Min. Typ.
Max. Min. Typ.
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
2. Specification for packaged product only.
PRODUCT ORDERING CODE
Ordering
Code
SY10E151JI
SY10E151JITR*
SY100E151JI
SY100E151JITR*
*Tape and Reel
Package
Type
J28-1
J28-1
J28-1
J28-1
Operating
Range
Industrial
Industrial
Industrial
Industrial
3
Micrel
SY10E151
SY100E151
28 LEAD PLCC (J28-1)
Rev. 03
MICREL, INC.
TEL
1849 FORTUNE DRIVE SAN JOSE, CA 95131
FAX
USA
+ 1 (408) 944-0800
+ 1 (408) 944-0970
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel, Inc.
