TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
hmp
Description
2M x 8 SRAM MODULE
SYS82000RKXD - 70/85/10/12
Issue 1.3 : February 2000
Features
Access Times of 70/85/100/120ns.
36 Pin Industry Standard Single-In-Line package.
5 Volt Supply ± 10% .
Power Dissipation :
Operating (min cycle)
Standby -L Version (CMOS)
Completely Static Operation.
Equal Access and Cycle Times.
Low Voltage V
CC
Data Retention.
Directly TTL Compatible.
On-board Decoding & Capacitors.
Compatible with the SYS8512RKX, SYS81000RKXB
and SYS82000RKX modules.
610 mW (max).
2.2 mW (max).
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England. Tel. +44 (0191) 2930500. Fax. +44 (0191)
2590997
The SYS82000RKXD is a plastic 16Mbit Static
RAM Module housed in a standard 36 pin Single-In-
Line package organised as 2M x 8. This offers an
extremely high PCB packing density.
The module is constructed using four 512Kx8
SRAMs in TSOPII packages mounted on a FR4
epoxy substrate. Access times are 70, 85, 100 and
120ns.
The SYS82000RKXD is offered in standard and
low power versions, with the -L module having a low
voltage data retention mode for battery backed
applications.
Block Diagram
A0~A18
D0~7
/WE
/OE
Pin Definition
A20
Vcc
WE
D2
D3
D0
A1
A2
A3
A4
GND
D5
A10
A11
A5
A13
A14
A19
CS
A15
A16
A12
A18
A6
D1
GND
A0
A7
A8
A9
D7
D4
D6
A17
Vcc
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
/CS
/CS
/CS
/CS
/CS
A19
A20
Decoder
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0 - A20
D0 - D7
CS
WE
OE
NC
V
CC
GND
Package Details
Plastic 36 Pin Single-In-Line (SIP)
SYS82000RKXD - 70/85/10/12
Issue 1.3 February 2000
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Symbol
V
T(2)
P
T
T
STG
Min
-0.3
-
-55
Typ
-
4.0
-
Max
7.0
-
125
Unit
V
W
o
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2) V
T
can be -3.0V pulse of less than 30ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
Min
4.5
2.2
-0.3
0
-40
Typ
5.0
-
-
-
-
Max
5.5
V
CC
+0.3
0.8
70
85
Unit
V
V
V
o
C
o
C
(Commercial)
(Industrial)
DC Electrical Characteristics
(V
CC
=5V±10%)
Parameter
I/P Leakage Current
T
A
0 to 70
o
C
Min Typ
-4
-4
-
-
-
-
-
2.4
-
-
-
-
-
-
-
-
max
4
4
110
12
8
400
0.4
-
Unit
µA
µA
mA
mA
mA
µA
V
V
Symbol Test Condition
Address,OE,WE
I
LI
I
LO
I
CC1
0V < V
IN
< V
CC
CS = V
IH,
V
I/O
= GND to V
CC
Min. Cycle, CS = V
IL
,V
IL
<V
IN
<V
IH
CS = V
IH
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V
I
OL
= 2.1mA
I
OH
= -1.0mA
Output Leakage Current
Average Supply Current
Standby Supply Current
TTL levels
CMOS levels
-L Version (CMOS)
I
SB1
I
SB2
I
SB3
V
OL
V
OH
Output Voltage
Typical values are at V
CC
=5.0V,T
A
=25
o
C and specified loading.
Capacitance
(V
CC
=5V±10%,T
A
=25
o
C)
Parameter
Input Capacitance
(Address,OE,WE)
I/P Capacitance
(other)
I/O Capacitance
C
IN1
C
IN2
C
I/O
Note: Capacitance calculated, not measured.
Symbol Test Condition
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
max
32
8
40
Unit
pF
pF
pF
2
SYS82000RKXD - 70/85/10/12
Issue 1.3 February 2000
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
CC
=5V±10%
I/O Pin
645
Ω
1.76V
100pF
Operation Truth Table
CS
H
L
L
L
L
OE
X
L
H
L
H
WE
X
H
L
L
H
DATA PINS
High Impedance
Data Out
Data In
Data In
High-Impedance
SUPPLY CURRENT
I
SB1
, I
SB2
, I
SB3
I
CC1
I
CC1
I
CC1
I
SB1
, I
SB2
, I
SB3
MODE
Standby
Read
Write
Write
High-Z
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
Low V
cc
Data Retention Characteristics - L Version Only
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Symbol
V
DR
I
CCDR1 (2)
t
CDR
t
R
Test Condition
CS > V
CC
-0.2V
V
CC
= 3.0V, CS > V
CC
-0.2V
T
OP
= 0°C to 40°C
See Retention Waveform
See Retention Waveform
min
2.0
-
0
5
typ
(1)
-
-
-
-
max
-
200
-
-
Unit
V
µA
ns
ms
Operation Recovery Time
Notes
(1) Typical figures are measured at 25°C.
(2) This parameter is guaranteed not tested.
3
SYS82000RKXD - 70/85/10/12
Issue 1.3 February 2000
AC OPERATING CONDITIONS
Read Cycle
-70
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
min
70
-
-
-
10
10
5
0
0
max
-
70
70
35
-
-
-
25
25
-85
min
85
-
-
-
10
10
5
0
0
max
-
85
85
45
-
-
-
30
30
-10
min
100
-
-
-
10
10
5
0
0
max
-
100
100
50
-
-
-
35
35
-12
min
120
-
-
-
10
10
5
0
0
max
-
120
120
60
-
-
-
45
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
-70
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
min
70
60
60
0
50
3
0
30
0
5
max
-
-
-
-
-
-
25
-
-
-
min
85
75
75
0
55
3
0
35
0
5
-85
max
-
-
-
-
-
-
30
-
-
-
min
100
80
80
0
60
3
0
40
0
5
-10
max
-
-
-
-
-
-
35
-
-
-
min
120
100
100
0
70
3
0
45
0
5
-12
max
-
-
-
-
-
-
40
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
SYS82000RKXD - 70/85/10/12
Issue 1.3 February 2000
Read Cycle Timing Waveform
(1,2)
t
RC
Address
t
AA
OE
t
OE
t
OLZ
t
OH
CS
t
ACS
t
CLZ (4,5)
t
OHZ (3)
Don't
care.
Dout
Data Valid
t
CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, t
CHZ
(max) is less than t
CLZ
(min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
(1,4)
t
WC
Address
t
WR(7)
OE
t
AS(6)
t
AW
t
CW
CS
Don't
Care
WE
t
OHZ(3,9)
t
WP(2)
High-Z
t
DW
t
DH
t
OW
(8)
Dout
High-Z
Din
Data Valid
5
