TC554161AFT-70,-85,-10,-70L,-85L,-10L
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT STATIC RAM
DESCRIPTION
The TC554161AFT is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16bits.
Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V
±
10%
power supply. Advanced circuit technology provides both high speed and low power at an operating current of 10
mA/MHz (typ) and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 2
mA
standby
current (typ) when chip enable (
CE
) is asserted high. There are two control inputs.
CE
is used to select the device
and for data retention control, and output enable (
OE
) provides fast memory access. Data byte control pin (
LB
,
UB
) provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. The TC554161AFT is available in a plastic 54-pin
thin-small-outline package (TSOP).
FEATURES
·
·
·
·
·
·
Low-power dissipation
Operating: 55 mW/MHz (typical)
Single power supply voltage of 5 V
±
10%
Power down features using
CE
.
Data retention supply voltage of 2 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Standby Current (maximum):
TC554161AFT
-70,-85,-10
5.5 V
3.0 V
100
mA
50
mA
-70L,-85L,-10L
50
mA
25
mA
·
Access Times (maximum):
TC554161AFT
-70,-70L
Access Time
CE
Access Time
OE
Access Time
-85,-85L
85 ns
85 ns
45 ns
-10,-10L
100 ns
100 ns
50 ns
70 ns
70 ns
35 ns
·
Package:
TSOP II54-P-400-0.80 (AFT) (Weight: 0.57 g typ)
PIN ASSIGNMENT
(TOP VIEW)
NC
A3
A2
A1
A0
I/O16
I/O15
V
DD
GND
I/O14
I/O13
UB
CE
OP
R/W
I/O12
I/O11
GND
V
DD
I/O10
I/O9
NC
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A4
A5
A6
A7
NC
I/O1
I/O2
V
DD
GND
I/O3
I/O4
LB
OE
OP
NC
I/O5
I/O6
GND
V
DD
I/O7
I/O8
A8
A9
A10
A11
A12
NC
PIN NAMES
A0~A17
I/O1~I/O16
CE
Address Inputs
Data Inputs/Outputs
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Power (+5 V)
Ground
No Connection
Option
R/W
OE
LB
,
UB
V
DD
GND
NC
OP*
*:
OP pin must be open of connected to GND.
(Normal pinout)
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TC554161AFT-70,-85,-10,-70L,-85L,-10L
BLOCK DIAGRAM
CE
A0
A1
A2
A3
A11
A12
A13
A14
A15
A16
A17
ROW ADDRESS
BUFFER
ROW ADDRESS
REGISTER
ROW ADDRESS
DECODER
MEMORY CELL ARRAY
2,048
´
128
´
16
(4,194,304)
V
DD
GND
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
SENSE AMP
DATA
OUTPUT
BUFFER
DATA
INPUT
BUFFER
COLUMN ADDRESS
DECODER
COLUMN ADDERSS
REGISTER
COLUMN ADDRESS
BUFFER
CE
A4 A5 A6 A7 A8 A9 A10
CLOCK
GENERATOR
R/W
OE
UB
LB
CE
CE
MAXIMUM RATINGS
SYMBOL
V
DD
V
IN
V
I/O
P
D
T
solder
T
stg
T
opr
Power Supply Voltage
Input Voltage
Input/Output Voltage
Power Dissipation
Soldering Temperature (10s)
Storage Temperature
Operating Temperature
RATING
VALUE
-
0.3~7.0
-
0.3
*
~7.0
-
0.5~V
DD
+
0.5
DATA
OUTPUT
BUFFER
DATA
INPUT
BUFFER
UNIT
V
V
V
W
°C
°C
°C
0.6
260
-
55~150
0~70
*
:
-
3.0 V when measured at a pulse width of 30ns
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TC554161AFT-70,-85,-10,-70L,-85L,-10L
DC RECOMMENDED OPERATING CONDITIONS
(Ta
=
0° to 70°C)
SYMBOL
V
DD
V
IH
V
IL
V
DH
*
:
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
Data Retention Supply Voltage
MIN
4.5
2.2
-
0.3
*
TYP
5.0
¾
¾
¾
MAX
5.5
V
DD
+
0.3
0.8
5.5
UNIT
V
V
V
V
2.0
-
3.0 V when measured at a pulse width of 30 ns
DC CHARACTERISTICS
(Ta
=
0° to 70°C, V
DD
=
5 V
±
10%)
SYMBOL
I
IL
I
LO
I
OH
I
OL
PARAMETER
Input Leakage
Current
Output Leakage
Current
Output High Current
Output Low Current
V
IN
=
0 V~V
DD
CE
=
V
IH
or R/W
=
V
IL
or
OE
=
V
IH
, V
OUT
=
0 V~V
DD
TEST CONDITION
MIN
¾
¾
-
1.0
TYP
¾
¾
¾
¾
¾
¾
MAX
±
1.0
±
1.0
¾
¾
UNIT
m
A
m
A
V
OH
=
2.4 V
V
OL
=
0.4 V
CE
=
V
IL
and R/W
=
V
IH
,
I
OUT
=
0 mA,
Other Input
=
V
IH
/V
IL
mA
mA
2.1
t
cycle
=
70 ns
t
cycle
=
85 ns, 100 ns
t
cycle
=
1
m
s
¾
¾
¾
¾
¾
¾
¾
110
100
¾
I
DDO1
Operating Current
I
DDO2
mA
15
¾
¾
t
cycle
=
70 ns
CE
=
0.2 V and R/W
=
V
DD
-
0.2 V,
I
OUT
=
0 mA,
t
cycle
=
85 ns, 100 ns
Other Input
=
V
DD
-
0.2 V/0.2 V
t
cycle
=
1
m
s
CE
=
V
IH
100
90
¾
mA
10
¾
I
DDS1
3
¾
mA
-70,-85,-10
Standby Current
I
DDS2
CE
=
V
DD
-
0.2 V,
V
DD
=
2.0 V~5.5 V
Ta
=
25°C
Ta
=
0~70°C
Ta
=
25°C
Ta
=
0~70°C
¾
¾
¾
¾
2
¾
100
5
50
m
A
2
¾
-70L,-85L,-10L
CAPACITANCE
(Ta
=
25°C, f
=
1 MHz)
SYMBOL
C
IN
C
OUT
Note:
PARAMETER
Input Capacitance
Output Capacitance
V
IN
=
GND
V
OUT
=
GND
TEST CONDITION
MAX
10
10
UNIT
pF
pF
This parameter is periodically sampled and is not 100% tested.
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TC554161AFT-70,-85,-10,-70L,-85L,-10L
OPERATING MODE
MODE
CE
OE
R/W
LB
UB
I/O1~I/O8
Output
High-Z
Output
Input
High-Z
Input
High-Z
I/O9~I/O16
Output
Output
High-Z
Input
Input
High-Z
High-Z
High-Z
POWER
I
DDO
I
DDO
I
DDO
I
DDO
I
DDO
I
DDO
I
DDO
I
DDS
L
Read
L
L
H
H
L
L
Write
L
*
L
L
H
L
L
H
*
L
H
L
L
Output Deselect
L
Standby
*
= don't care
H = logic high
L = logic low
H
*
*
H
*
*
*
H
*
H
*
H
High-Z
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TC554161AFT-70,-85,-10,-70L,-85L,-10L
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
=
0° to 70°C, V
DD
=
5 V
±
10%)
READ CYCLE
TC554161AFT
SYMBOL
PARAMETER
-70,-70L
MIN
t
RC
t
ACC
t
CO
t
OE
t
BA
t
OH
t
COE
t
OEE
t
BE
t
OD
t
ODO
t
BD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Data Byte Control Access Time
Output Data Hold Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
70
¾
¾
¾
¾
-85,-85L
MIN
85
¾
¾
¾
¾
-10,-10L
MIN
100
¾
¾
¾
¾
UNIT
MAX
¾
MAX
¾
MAX
¾
70
70
35
35
¾
¾
¾
¾
85
85
45
45
¾
¾
¾
¾
100
100
50
50
¾
¾
¾
¾
10
10
5
5
¾
¾
¾
10
10
5
5
¾
¾
¾
10
10
5
5
¾
¾
¾
ns
25
25
25
30
30
30
35
35
35
WRITE CYCLE
TC554161AFT
SYMBOL
PARAMETER
-70,-70L
MIN
t
WC
t
WP
t
CW
t
BW
t
AS
t
WR
t
DS
t
DH
t
OEW
t
ODW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Time
Write Recovery Time
Data Setup Time
Data Hold Time
R/W High to Output Active
R/W Low to Output High-Z
70
50
60
50
0
0
30
0
5
¾
-85,-85L
MIN
85
55
70
55
0
0
35
0
5
¾
-10,-10L
MIN
100
60
80
60
0
0
40
0
5
¾
UNIT
MAX
¾
¾
¾
¾
¾
¾
¾
¾
¾
MAX
¾
¾
¾
¾
¾
¾
¾
¾
¾
MAX
¾
¾
¾
¾
¾
¾
¾
¾
¾
ns
25
30
35
AC TEST CONDITIONS
PARAMETER
Output load
Input pulse level
Timing measurements
Reference level
t
R
, t
F
TEST CONDITION
100 pF
+
1 TTL Gate
0.6 V, 2.4 V
1.5 V
1.5 V
5 ns
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